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NB4N1158DTR2G

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2007
December, 2007 - Rev. 0
1 Publication Order Number:
NB4N1158/D
NB4N1158
Link Replicator for Fibre
Channel, Gigabit Ethernet,
HDTV and SATA
Up to 1.5 Gb/s
Description
The NB4N1158 is a high performance 3.3 V Serial Link Replicator
which provides the function of serial loop replication and serial
loopback control commonly required in Fibre Channel, GbE, HDTV
and SATA applications. Other popular applications include Host Bus
Adaptors for routing between internal and external connectors, and
hot-pluggable links between redundant switch fabric cards.
IN is sent to both OUT0 and OUT1; each output is enabled by OE0
and OE1 when HIGH. OUT0 can select either IN or IN1 via the
MUX0 pin. Likewise, OUT1 can select between IN or IN0 via the
MUX1 pin. Out can select between IN0 and IN1.
In Link Replicator applications, such as the Line Card to Switch
Card links, IN is transmitted to both OUT0 and OUT1 which either
IN0 or IN1 is selected at OUT. In Host Adapter applications, IN goes
to OUT0 (an internal connector) which returns data on IN0. IN0 is
looped to OUT1 (an external connector) which returns data on IN1 and
then back to the SerDes on OUT.
The NB4N1158 is packaged in a 4.7 mm x 9.7 mm TSSOP-28.
Features
•Replicates Fibre Channel, Gigabit Ethernet, HDTV, and
Serial ATA (SATA) Links
•T11 Fibre Channel Complaint at 1.0625 Gb/s
•Differential LVPECL Outputs, External Load/Termination
Resistors Required
•IEEE802.3z Gigabit Ethernet Compliant at 1.25 Gb/s
•SMPTE-292M Compliant at 1.485 Gb/s
•330 mW Maximum Power Dissipation
•Operating Range: V
CC
= 3.135 V to 3.465 V
•28-pin, 4.4 mm x 9.7 mm TSSOP Package
•These are Pb-Free Devices
MARKING DIAGRAM*
28 Lead TSSOP
DT SUFFIX
CASE 948A
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
NB4N
1158
ALYW
Figure 1. Simplified Application
TX
RX
LOOP0
LOOP1
NB4N1158
NB4N1158
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2
TYPICAL APPLICATIONS CIRCUIT
Figure 2. Simplified Block Diagram
0
1
OUT+
OUT-
MUX
IN+
IN-
OUT1+
OUT1-
MUX1
OE1
IN1+
IN1-
MUX0
OUT0+
OUT0-
OE0
IN0+
IN0-
0
1
0
1
Figure 3. Pin Diagram for TSSOP-28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDP0
OE0
MUX
GND
IN+
IN-
GND
OE1
VDD
VDDP
OUT+
OUT-
VDDP
GND
OUT0+
OUT0-
VDDP0
GND
IN0+
IN0-
VDDP1
OUT1+
OUT1-
VDDP1
IN1+
IN1-
MUX0
MUX1
NB4N1158
Table 1. OE, OUTPUT ENABLE FUNCTION
OEx* Function
1 Outputs Enabled
0 Outputs Disabled OUTn+ = H, OUTn- = H
*Defaults to HIGH when left open
Table 2. PIN DESCRIPTION
Pin Name I/O Description
5, 6
24, 23
18, 17
IN+, IN-
IN0+, IN0-
IN1+, IN1-
LVPECL Input
LVPECL Input
LVPECL Input
Non-inverted, Inverted, Differential Data Inputs internally biased to
Approximately 1.2 V.
11, 12
28, 27
21, 20
OUT+, OUT-
OUT0+, OUT0-
OUT1+, OUT1-
LVPECL Output
LVPECL Output
LVPECL Output
Non-inverted, Inverted Differential Outputs. Typically terminated with 50
resistor to V
CC
- 2.0 V.
2
8
OE0
OE1
LVTTL Input
LVTTL Input
OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx are
powered down and both OUT+ and OUT- float HIGH.
3 MUX LVTTL Input Selects Source for OUT, Selects Either IN0 (LOW) or IN1 (HIGH); defaults
HIGH when left open.
15 MUX1 LVTTL Input Selects Source for OUT1. Selects Either IN (HIGH) or IN0 (LOW); defaults
HIGH when left open.
16 MUX0 LVTTL Input Selects Source for OUT0. Selects either IN (LOW) or IN1 (HIGH); defaults
HIGH when left open.
9 VDD Power Supply 3.3 V Positive Supply Voltage for Digital Logic.
10, 13
1, 26
19, 22
VDDP
VDDP0
VDDP1
Power Supply 3.3 V supply for LVPECL output drivers. VDDP is for OUT, VDDP0 is for
OUT0, and VDDP1 is for OUT1.
4, 7, 14, 25 GND Power Supply Negative Supply Voltage, Connected to Ground
All VDD, VDDPx and GND Pins must be externally connected to appropriate power supply to guarantee proper operation.
NB4N1158
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3
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pullup Resistor
96 k
ESD Protection Human Body Model
Machine Model
> 1 kV
> 100 V
Moisture Sensitivity (Note 1) Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 268 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Min Max Unit
V
DD
Positive Power Supply GND = 0 V 0.5 4.0 V
V
INP
Input Voltage, PECL GND = 0 V -0.5 V
DD
+ 0.5 V
V
INT
Input Voltage, TTL GND = 0 V -0.5 V
DD
+ 0.5 V
I
OUT
Output HIGH current, PECL -50 +50 mA
T
C
Case temperature under bias -55 +125 °C
TA Operating Temperature Range -40 +85 °C
T
stg
Storage Temperature Range -65 +150 °C
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP-28 76
60
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case) (Note 2) TSSOP-28 25 °C/W
T
sol
Wave Solder Pb-Free 265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
P1-P3P4-P6P7-P8

NB4N1158DTR2G

Mfr. #:
Buy NB4N1158DTR2G
Manufacturer:
ON Semiconductor
Description:
Interface - Specialized 2.5 GBPS SER LNK REP
Lifecycle:
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