NB4N1158DTR2G

NB4N1158
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Table 5. DC CHARACTERISTICS V
DD
= 3.30 V $5%, GND = 0 V; T
A
= -40°C to +85°C (Note 3)
Symbol Characteristic Min Typ Max Unit
V
DD
Power Supply Voltage, 3.30 V $5% 3.14 3.47 V
I
DD
Power Supply Current (Outputs open) 57 75 mA
P
D
Power Dissipation; Outputs Open; V
DD
= V
DDmax
330 mW
V
IN
Receiver Differential Voltage Amplitude; (IN, IN0, IN1), AC-Coupled,
Internally Biased to 1.2 V; Differential Measurement - (V
INn+
- V
INn-
) 300 2600
mV
V
OUT50
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 50 to V
DD
– 2.0 V
Differential Measurement - (V
OUTn+
- V
OUTn-
)
1000 1600 2200
mV
V
OUT75
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 75 to V
DD
– 2.0 V
Differential Measurement - (V
OUTn+
- V
OUTn-
)
1200 1650 2200
mV
LVCMOS/LVTTL INPUTS
V
IH
Input HIGH Voltage, TTL 2.0 V
DD
+ 0.5 V
V
IL
Input LOW Voltage, TTL 0 0.8 V
I
IH
Input HIGH Current, TTL; V
IN
= 2.4 V 100
A
I
IL
Input LOW Current, TTL; V
IN
= 0.5 V -100
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. LVPECL outputs loaded with external 50 termination resistors to V
TT
= V
DD
- 2.0 V for proper operation (see Figure 6).
Table 6. AC CHARACTERISTICS V
DD
= 3.3 V $5%, GND = 0 V -40°C to +85°C
Symbol Characteristic Min Typ Max Unit
f
IN
/
OUT
Input / Output Frequency Range 1.0 1.5 Gb/s
tr/tf Output rise and Fall Times (Note 4) 110 150 ps
t
PD
Propagation Delay, IN to OUT 0.375 4.0 ns
T
DJ
Deterministic Jitter Added to Serial Input Up to 1.5 Gb/s;
K28.5$ Pattern
40 ps pk-pk
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured 20% to 80%
Figure 4. Timing Waveforms
IN1+/-
OUT+/-
IN0+/-
IN+/-
OUT0+/-
OUT1+/-
t
pd
t
pd
t
J
NB4N1158
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Figure 5. NB4N1158 Application Interface Example
NB4N1158 NB4N1158 SerDesSerDes
TX+
TX-
RX+
RX-
O1+
O1-
I1+
I1-
I+
I-
O+
O-
O+
O-
I+
I-
I1+
I1-
O1+
O1-
RX+
RX-
TX+
TX-
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
R
R
RT
R
R
R
R
R
R
R
R
R
R
RT RT RT
RT RT
“R” is 150 for both 100 differential or 150 differential traces.
“RT” matches the differential impedance of the link.
IN+/IN- Input Functionality
The differential inputs are internally biased to Y1.2 V. In
a typical application, the differential inputs are
capacitor-coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N1158 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT- Outputs
The differential output buffers of the NB4N1158 utilize
standard Positive Emitter Coupled Logic (PECL)
architecture for OUT+ and OUT-. The outputs are designed
to drive differential transmission lines with nominally 50
or 75 characteristic impedance. External
DC load/termination with a 50 resistor to V
TT
= V
DD
-
2.0 V is required. See Figure 6 for output termination
scheme.
OEx Output Enable
The NB4N1158 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in I
DD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx- are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N1158 provides separate power supply
pins for the digital circuitry (V
DD
) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01 F to 0.1 F
on each VDD pin will help ensure a noise free V
DD
power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50
Z
o
= 50
50 50
V
TT
V
TT
= V
CC
- 2.0 V
NB4N1158
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Resource Reference of Application Notes
AND8002 - Marking and Date Codes
AND8009 - ECLinPS Plus Spice I/O Model Kit
AND8020 - Termination of ECL Logic Devices
ORDERING INFORMATION
Device Package Shipping
NB4N1158DTG TSSOP-28
(Pb-Free)
50 Units / Rail
NB4N1158DTR2G TSSOP-28
(Pb-Free)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

NB4N1158DTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Interface - Specialized 2.5 GBPS SER LNK REP
Lifecycle:
New from this manufacturer.
Delivery:
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