IDT6P61033
8-OUTPUT SMALL FORM FACTOR PCIE GEN1-2-3 BUFFER
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN1-2-3 BUFFER 6
IDT6P61033 REV A 022513
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT6P61033. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
1.8V Supply Voltage VDDxx Applies to VDD, VDDA and VDDIO -0.5 2.5 V 1,2
Input Voltage V
IN
DD
+0.5V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
COM
or T
IND;
Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
IHDI F
Differential inputs
(sin
le-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1,3
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 725 mV 1
Input Amplitude - DIF_IN V
SWING
IHDI F
ILDI
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 V/ns 1,2
IN
IN
DD ,
IN
= GND -5 0.01 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 150 ps 1
1
Guaranteed by desi
n and characterization, not 100% tested in production.
Slew rate measured throu
h +/-75mV window centered around differential zero
3
The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the V
BIAS
, where V
BIAS
is (V
IHHIGH
IHLOW
