IDT6P61033
8-OUTPUT SMALL FORM FACTOR PCIE GEN1-2-3 BUFFER
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN1-2-3 BUFFER 9
IDT6P61033 REV A 022513
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL
Characterisitics
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in Hi
h BW Mode 2 2.7 4 MHz 1,5
-3dB point in Low BW Mode 1 1.4 2 MHz 1,5
JPEAK
Peak Pass band Gain 1.2 2 dB 1
Duty Cycle t
D
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -1 0 1 % 1,3
t
dBYP
= 50% 3000 3600 4500 ps 1
t
dPLL
= 50% 0 92 200 ps 1,4
Skew, Output to Output t
sk3
PLL mode 16 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 25 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
The MIN/TYP/MAX values of each BW settin
track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
PLL Bandwidth BW
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
TA = T
COM
or T
IND;
Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
hPCIeG1
PCIe Gen 1 34 52 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 1.4 3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.2
2.5 3.1
ps
(rms)
1,2
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
(rms)
1,2,4
t
jphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9 2 NA
ps
(rms)
1,6
t
jphPCIeG1
PCIe Gen 1 0.6 5 N/A ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.3 N/A
ps
(rms)
1,2,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.05 0.1 N/A
ps
(rms)
1,2,5
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.05 0.1 N/A
ps
(rms)
1,2,4,
5
t
jphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
0.15 0.3 N/A
ps
(rms)
1,6
1
Applies to all outputs, with device driven by 9FG432AKLF or equivalent.
5
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
6
Applies to all differential outputs
4
Subject to final radification by PCI SIG.
3
Sample size of at least 100K cycles. This fi
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Additive Phase Jitter,
Bypass Mode
t
jphPCIeG2
2
See http://www.pcisig.com for complete specs
Phase Jitter, PLL Mode
t
jphPCIeG2