ISL6744AABZ Datasheet ISL6744AABZ, ISL6744AAUZ, ISL6744AAUZ-T | P7-P9

FN6554.0

October 8, 2007

Pin Descriptions

- V

is the power connection for the IC. To optimize

noise immunity, bypass V

to GND with a ceramic

capacitor as close to the V

and GND pins as possible.

The total supply current, I

, will be dependent on the load

applied to outputs OUTA and OUTB. Total I

current is the

sum of the quiescent current and the average output current.

Knowing the operating frequency (Fsw) and the output

loading capacitance charge (Q) per output, the average

output current can be calculated from Equation 1:

- This is the oscillator timing capacitor discharge current

control pin. A resistor is connected between this pin and

GND. The current flowing through the resistor determines

the magnitude of the discharge current. The discharge

current is nominally 55x this current. The PWM deadtime is

determined by the timing capacitor discharge duration.

- The oscillator timing capacitor is connected between

this pin and GND.

CS - This is the input to the overcurrent protection comparator.

The overcurrent comparator threshold is set at 0.600V nominal.

The CS pin is shorted to GND at the end of each switching

cycle. Depending on the current sensing source impedance, a

series input resistor may be required due to the delay between

the internal clock and the external power switch.

Exceeding the overcurrent threshold will start a delayed

shutdown sequence. Once an overcurrent condition is

detected, the soft-start charge current source is disabled.

The soft-start capacitor begins discharging through a 15µA

current source, and if it discharges to less than 3.9V

(Sustained Overcurrent Threshold), a shutdown condition

occurs and the OUTA and OUTB outputs are forced low.

When the soft-start voltage reaches 0.27V (Reset

Threshold) a soft-start cycle begins.

If the overcurrent condition ceases, and then an additional

50µs period elapses before the shutdown threshold is

reached, no shutdown occurs. The SS charging current is

re-enabled and the soft-start voltage is allowed to recover.

GND - Reference and power ground for all functions on this

device. Due to high peak currents and high frequency

operation, a low impedance layout is necessary. Ground

planes and short traces are highly recommended.

OUTA and OUTB - Alternate half cycle output stages. Each

output is capable of 1A peak currents for driving power

MOSFETs or MOSFET drivers. Each output provides very

low impedance to overshoot and undershoot.

SS - Connect the soft-start timing capacitor between this pin

and GND to control the duration of soft-start. The value of the

capacitor determines the rate of increase of the duty cycle

during start-up, controls the overcurrent shutdown delay, and

the overcurrent and short circuit hiccup restart period.

Functional Description

Features

The ISL6744A PWM is an excellent choice for low cost

bridge topologies for applications requiring accurate

frequency and deadtime control. Among its many features

are 1A FET drivers, adjustable soft-start, overcurrent

protection and internal thermal protection, allowing a highly

flexible design with minimal external components.

Oscillator

The ISL6744A has an oscillator with a frequency range to

2MHz, programmable using a resistor R

and capacitor C

The switching period may be considered to be the sum of

the timing capacitor charge and discharge durations. The

charge duration is determined by C

and the internal current

source (assumed to be 160

μA in the formula). The discharge

duration is determined by R

and C

where T

and T

are the approximate charge and discharge

times, respectively, T

OSC

is the oscillator free running

period, and F

OSC

is the oscillator frequency. One output

switching cycle requires two oscillator cycles. The actual

times will be slightly longer than calculated due to internal

propagation delays of approximately 5ns/transition. This

delay adds directly to the switching duration, and also

causes overshoot of the timing capacitor peak and valley

voltage thresholds, effectively increasing the peak-to-peak

voltage on the timing capacitor. Additionally, if very low

charge and discharge currents are used, there will be an

increased error due to the input impedance at the C

pin.

The above formulae help with the estimation of the

frequency. Practically, effects like stray capacitances that

affect the overall C

capacitance, variation in R

voltage

and charge current over temperature, etc. exist, and are best

evaluated in-circuit. Equation 2 follows from the basic

capacitor current equation, . In this case, with

variation in dV with R

(Figure 5), and in charge current

(Figure 4), results from Equation 2 would differ from the

calculated frequency. The typical performance curves may

be used as a tool along with the above equations as a more

accurate tool to estimate the operating frequency more

accurately.

The maximum duty cycle (D) and deadtime (DT) can be

calculated from Equations 5 and 6:

OUT

2QFsw••=

(EQ. 1)

1.25

×10 C

•≈ s

(EQ. 2)

CTDisch eCurrentGainarg

-----------------------------------------------------------------------------

• C

•≈ s

(EQ. 3)

OSC

----------------

== s(EQ. 4)

×=

OSC

⁄= (EQ. 5)

DT 1 D–()T

OSC

⋅= s(EQ. 6)

ISL6744A

FN6554.0

October 8, 2007

Soft-Start Operation

The ISL6744A features a soft-start using an external

capacitor in conjunction with an internal current source. Soft-

start reduces stresses and surge currents during start-up.

The oscillator capacitor signal (C

) is compared to the

soft-start voltage (SS) in the SS comparator which drives the

PWM latch. While the SS voltage is less than 3.5V, duty

cycle is limited. The output pulse width increases as the

soft-start capacitor voltage increases up to 3.5V. This has

the effect of increasing the duty cycle from zero to the

maximum pulse width during the soft-start period. When the

soft-start voltage exceeds 3.5V, soft-start is completed.

Soft-start occurs during start-up and after recovery from an

overcurrent shutdown. The soft-start voltage is clamped

to 4V.

Gate Drive

The ISL6744A is capable of sourcing and sinking 1A peak

current, and may also be used in conjunction with a

MOSFET driver such as the ISL6700 for level shifting. To

limit the peak current through the IC, an external resistor

may be placed between the totem-pole output of the IC

(OUTA or OUTB pin) and the gate of the MOSFET. This

small series resistor also damps any oscillations caused by

the resonant tank of the parasitic inductances in the traces of

the board and the FET’s input capacitance.

Overcurrent Operation

Overcurrent delayed shutdown is enabled once the soft-start

cycle is complete. If an overcurrent condition is detected, the

soft-start charging current source is disabled and the soft-

start capacitor is allowed to discharge through a 15µA

source. At the same time a 50µs retriggerable one-shot timer

is activated. It remains active for 50µs after the overcurrent

condition ceases. If the soft-start capacitor discharges to

3.9V, the output is disabled. This state continues until the

soft-start voltage reaches 270mV, at which time a new soft-

start cycle is initiated. If the overcurrent condition stops at

least 50µs prior to the soft-start voltage reaching 3.9V, the

soft-start charging currents revert to normal operation and

the soft-start voltage is allowed to recover.

Thermal Protection

An internal temperature sensor protects the device should

the junction temperature exceed +145°C. There is

approximately +15°C of hysteresis.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

device. A good ground plane must be employed. V

should

be bypassed directly to GND with good high frequency

capacitance.

Typical Application

The Typical Application Schematic features the ISL6744A in

an unregulated half-bridge DC/DC converter configuration,

often referred to as a DC Transformer or Bus Converter.

The input voltage is 48V ±10% DC. The output is a nominal

12V when the input voltage is at 48V. Since this is an

unregulated topology, the output voltage will vary

proportionately with input voltage. The load regulation is a

function of resistance between the source and the converter

output. The output is rated at 8A.

Circuit Elements

The converter design is comprised of the following functional

blocks:

Input Filtering: L1, C1, R1

Half-Bridge Capacitors: C2, C3

Isolation Transformer: T1

Primary Snubber: C13, R10

Start Bias Regulator: CR3, R2, R7, C6, Q5, D1

Supply Bypass Components: C15, C4

Main MOSFET Power Switch: QH, QL

Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10,

C14

Control Circuit: U1, C18, C16, D2

Output Rectification and Filtering: QR1, QR2, QR3, QR4,

L2, C9, C8

Secondary Snubber: R8, R9, C11, C12

FET Driver: U4

Bootstrap components for driver: CR4, C5

ZVS Resonant Delay (Optional): L3, C7

Design Specifications

The following design requirements were selected for

evaluation purposes:

Switching Frequency, Fsw: 235kHz

: 48 ± 10% V

OUT

: 12V (nominal)

OUT

: 8A (steady state)

OUT

: 100W

Efficiency: 95%

Ripple: 1%

ISL6744A

FN6554.0

October 8, 2007

Transformer Design

The design of a transformer for a half-bridge application is a

straightforward affair, although iterative. It is a process of

many compromises, and even experienced designers will

produce different designs when presented with identical

requirements. The iterative design process is not presented

here for clarity.

The abbreviated design process follows:

• Select a core geometry suitable for the application.

Constraints of height, footprint, mounting preference, and

operating environment will affect the choice.

• Determine the turns ratio.

• Select suitable core material(s).

• Select maximum flux density desired for operation.

• Select core size. Core size will be dictated by the

capability of the core structure to store the required

energy, the number of turns that have to be wound, and

the wire gauge needed. Often the window area (the space

used for the windings) and power loss determine the final

core size.

• Determine maximum desired flux density. Depending on

the frequency of operation, the core material selected, and

the operating environment, the allowed flux density must

be determined. The decision of what flux density to allow

is often difficult to determine initially. Usually the highest

flux density that produces an acceptable design is used,

but often the winding geometry dictates a larger core than

is indicated based on flux density alone.

• Determine the number of primary turns.

• Select the wire gauge for each winding.

• Determine winding order and insulation requirements.

• Verify the design.

For this application we have selected a planar structure to

achieve a low profile design. A PQ style core was selected

because of its round center leg cross section, but there are

many suitable core styles available.

Since the converter is operating open loop at nearly 100%

duty cycle, the turns ratio, N, is simply the ratio of the input

voltage to the output voltage divided by 2.

The factor of 2 in the denominator is due to the half-bridge

topology. Only half of the input voltage is applied to the

primary of the transformer.

A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from

TDK were selected for the transformer core. The ferrite

material is PC44.

The core parameter of concern for flux density is the

effective core cross-sectional area, Ae. For the PQ core

pieces selected:

Ae = 0.62cm

or 6.2e -5m

Using Faraday’s Law, V = N dΦ/dt, the number of primary

turns can be determined once the maximum flux density is

set. An acceptable Bmax is ultimately determined by the

allowable power dissipation in the ferrite material and is

influenced by the lossiness of the core, core geometry,

operating ambient temperature, and air flow. The TDK

datasheet for PC44 material indicates a core loss factor of

~400mW/cm

with a ± 2000 gauss 100kHz sinusoidal

excitation. The application uses a 235kHz square wave

excitation, so no direct comparison between the application

and the data can be made. Interpolation of the data is

required. The core volume is approximately 1.6cm

, so the

estimated core loss is

1.28W of dissipation is significant for a core of this size.

Reducing the flux density to 1200 gauss will reduce the

dissipation by about the same percentage, or 40%.

Ultimately, evaluation of the transformer’s performance in

the application will determine what is acceptable.

From Faraday’s Law and using 1200 gauss peak flux density

(ΔB = 2400 gauss or 0.24 tesla)

Rounding up yields 4 turns for the primary winding. The peak

flux density using 4 turns is ~1100 gauss. From EQ. 7, the

number of secondary turns is 2.

The volts/turn for this design ranges from 5.4V at V

= 43V

to 6.6V at V

= 53V. Therefore, the synchronous rectifier

(SR) windings may be set at 1 turn each with proper FET

selection. Selecting 2 turns for the synchronous rectifier

FIGURE 6. TRANSFORMER SCHEMATIC

OUT

2•

-------------------------

12 2•

---------------

2===

(EQ. 7)

loss

-----------

act

meas

---------------

•• 0.4 1.6

200kHz

100kHz

---------------------

••=≈ 1.28= W

(EQ. 8)

•

ΔB••

------------------------------

53210

6–

••

26.210

5–

0.24•••

-----------------------------------------------------

3.56== =turns

(EQ. 9)

ISL6744A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

ISL6744AABZ

Mfr. #:

Buy ISL6744AABZ

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers HI SPD DOUBLE ENDED CONT 8LD

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ISL6744AABZ

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