19
FN8120.2
November 26, 2007
Power-Up and Power-Down Timing
RESET
Output Timing
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Symbol Parameter Min. Typ. Max. Unit
V
TRIP
Reset Trip Point Voltage, X4163, X4165-4.5A
Reset Trip Point Voltage, X4163, X4165
Reset Trip Point Voltage, X4163, X4165-2.7A
Reset Trip Point Voltage, X4163, X4165-2.7
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
t
PURST
Power-up Reset Time Out 100 250 400 ms
t
RPD
(8)
V
CC
Detect to Reset/Output 500 ns
t
F
(8)
V
CC
Fall Time 100 µs
t
R
(8)
V
CC
Rise Time 100 µs
V
RVALID
Reset Valid V
CC
1V
V
CC
t
PURST
t
R
t
F
t
RPD
0 Volts
V
TRIP
RESET
RESET
V
RVALID
(X4165)
(X4163)
t
PURST
V
RVALID
t
RSP
<t
WDO
t
RST
RESET
SDA
t
RSP
Note: All inputs are ignored during the active reset period (t
RST
).
t
RST
SCL
t
RSP
>t
WDO
t
RSP
>t
WDO
X4163, X4165
20
FN8120.2
November 26, 2007
RESET Output Timing
V
TRIP
Programming Timing Diagram (WEL = 1)
V
TRIP
Programming Parameters
Symbol Parameter Min. Typ. Max. Units
t
WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
250
650
1.5
400
850
2
ms
ms
sec
t
RST
Reset Time Out 100 250 400 ms
Parameter Description Min. Max. Unit
t
VPS
V
TRIP
Program Enable Voltage Setup time 1 µs
t
VPH
V
TRIP
Program Enable Voltage Hold time 1 µs
t
TSU
V
TRIP
Setup time 1 µs
t
THD
V
TRIP
Hold (stable) time 10 ms
t
WC
V
TRIP
Write Cycle Time 10 ms
t
VPO
V
TRIP
Program Enable Voltage Off time (Between successive adjustments) 0 µs
t
RP
V
TRIP
Program Recovery Period (Between successive adjustments) 10 ms
V
P
Programming Voltage 15 18 V
V
TRAN
V
TRIP
Programmed Voltage Range 2.55 4.75 V
V
ta1
Initial V
TRIP
Program Voltage accuracy (V
CC
applied - V
TRIP
) (Programmed at 25°C.) -0.1 +0.4 V
V
ta2
Subsequent V
TRIP
Program Voltage accuracy [(V
CC
applied - V
ta1
) - V
TRIP
.
Programmed at 25°C.]
-25 +25 mV
V
tr
V
TRIP
Program Voltage repeatability (Successive program operations. Programmed
at 25°C.)
-25 +25 mV
V
tv
V
TRIP
Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV
V
TRIP
programming parameters are periodically sampled and are not 100% tested.
V
CC
(V
TRIP
)
WP
t
TSU
t
THD
t
VPH
t
VPS
V
P
V
TRIP
t
VPO
SCL
SDA
A0h
01h or 03h
t
RP
00h
00h
X4163, X4165
21
FN8120.2
November 26, 2007
X4163, X4165
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1
L
L1
DETAIL X
4° ±4°
SEATING
PLANE
e
H
b
C
0.010 BM CA
0.004 C
0.010 BM CA
B
D
(N/2)
1
E1
E
NN
(N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL SO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994

X4163S8I

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC CPU SUPRV 16K EE RST LO 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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