Lattice Semiconductor Turbo Encoder User’s Guide
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Introduction
This document contains technical information about the Lattice Turbo Encoder IP core.
Turbo coding is an advanced error correction technique widely used in the communications industry. The Turbo
Encoder IP Core offered by Lattice is compliant with three different standards: 3GPP, 3GPP2 and CCSDS.
The Turbo Encoder core comes with the following documentation and files:
• User’s Guide
• Lattice evaluation gate level netlist
• Evaluation model for simulation
• Core instantiation template
• Testbench and testbench coding template
Core Specification
Features
• Fully compatible with Third Generation Partnership Project (3GPP) standard:
– 3GPP TS 25.212 Version 4.2.0
• Fully compatible with Third Generation Partnership Project 2 (3GPP2) standard:
– 3GPP2 C.S0002-A
• Fully compatible with Consultative Committee for Space Data Systems standard:
– CCSDS 101.0-B-5
• Configurable input block sizes
• User defined number of states
• User parameterized forward and backward polynomials
• Programmable puncturing support
• Fixed processing delay of 12 cycles for CCSDS, 10 cycles for 3GPP, and 9 cycles for 3GPP2
General Description
Turbo encoders and decoders are key elements in today’s communication systems to achieve the best possible
data reception with least possible errors. Lattice’s Turbo Encoder IP Core is compliant with three different stan-
dards: 3GPP, 3GPP2, and CCSDS. The 3GPP and 3GPP2 standards are widely used in WCDMA and MC-CDMA
applications while CCSDS is most commonly used in telemetry and space communications. Each one of these
encoders is a separate entity as the interleaver and control logic for each encoder is completely different.
Lattice’s Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state
of the art error correction technique. For more information on Lattice products, refer to the Lattice website at
www.latticesemi.com.
