Lattice Semiconductor Turbo Encoder User’s Guide
5
Functional Description
The Turbo Encoder functions as a slave device with respect to the input source, which applies the inputs to the
encoder, as well as the output source, which takes the encoded data from the encoder. Data is fed through two
recursive systematic convolutional (RSC) encoders. Each RSC encoder contains the same structure but operates
on two different versions of data. The first encoder operates on an original copy of data, whereas the second
encoder operates on an “interleaved” version of data. Interleaving is the method in which bits are rearranged
according to a predefined algorithm.
The Lattice Turbo Encoder IP Core consists of four different modules: Control Module, Dual Port RAM, Encoder
Module and Interleaver Module.
Control Module
The control module takes care of the handshake and control signals necessary for communication between the
various blocks and I/O pins. The block size is determined by the user and input into the control module. Signal
cfgset
enables the data on
blocksize
to be latched into the encoder. In order for a change in
blocksize
to be
recognized,
cfgset
must be asserted.
Control signals
rfi
and
rfo
are generated to indicate when the Turbo Encoder is ready to accept new data and
ready to output encoded data.
rfi
is an active high signal and is activated only when the encoder is ready to
accept data. Once
rfi
goes low,
rfo
is asserted after a fixed processing delay to output encoded data. After data
on
din
is valid, signal
inpvalid
can be asserted by the user to allow the encoder to read data.
inpvalid
should
be asserted only when
rfi
is high except for the last data to be input. In the same manner signal
rfno
should be
asserted by the user to read encoded data only when
rfo
is high.
Signal
sr
can be used to reinitialize the Turbo Encoder in the middle of a block processing. This can be done at any
point of time during the operation of the encoder. If
sr
is asserted it should be followed by an initialization of
cfg-
set
to specify the
blocksize
and start the encoding process all over again. Input signal
rstn
is an asynchro-
nous reset. This clears all the flip-flops in the design.
Dual Port RAM and Interleaver Module
The dual port RAM module stores the incoming data block. Each memory size is equal to the data block size. After
the encoder receives all the data in a block, the interleaving process begins.
The interleaver module is required to randomize the bit positions in the block. The interleaver is a mapping between
input and output bit positions and involves a predefined algorithm that changes the position of the bits. This algo-
rithm is implemented in the interleaver module. Interleaving begins once a full block of data is received and stored
into the dual port RAM. All computation needed for interleaving is completed before any data comes in. A copy of
the incoming data goes directly to the first encoder while an interleaved copy goes to the second encoder.
The Lattice Turbo Encoder IP Core has a fixed processing delay which is smaller than most competing solutions.
Once the data is received, the encoder is ready (after the fixed processing delay) to output the encoded data. The
processing delay is not dependent on the block size selected.
Encoder Module
The encoder module consists of two recursive systematic convolutional (RSC) encoders. At the output of the two
encoders is a multiplexer, which selects the output from different paths depending upon the output rate specified. If
non-standard forward and reverse feedback connections are required, they may be implemented in the encoder by
user-defined forward and reverse polynomials.
