74LVC273_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 September 2013 9 of 16
NXP Semiconductors
74LVC273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
V
X
V
Y
1.2 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
1.65 V to 1.95 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.3 V to 2.7 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.7 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 8. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input Load V
EXT
V
CC
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.2 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
2.3 V to 2.7 V V
CC
2 ns 30 pF 500 open 2 V
CC
GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
