10
LT1776
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1776
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation, the actual maximum V
IN
achievable in
a particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
For example, while the combination of V
IN
= 40V, V
OUT
=
5V at 500mA and f
OSC
= 200kHz may be easily achievable,
simultaneously raising V
IN
to 60V and f
OSC
to 400kHz is
not possible. Nevertheless, input voltage
transients
up to
60V can usually be accommodated, assuming the result-
ing increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
A second consideration is controllability. A potential limi-
tation occurs with a high step-down ratio of V
IN
to V
OUT
,
as this requires a correspondingly narrow minimum switch
ON time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
M
VV
Vf
ON
OUT F
IN OSC
in t =
+
()
where:
V
IN
= input voltage
V
OUT
= output voltage
V
F
= Schottky diode forward drop
f
OSC
= switching frequency
It is important to understand the nature of minimum
switch ON time as given in the data sheet. This test is
intended to mimic behavior under short-circuit condi-
tions. It is performed with the V
C
control voltage at its
clamp level (V
CL
) and uses a fixed resistive load from V
SW
to ground for simplicity. The resulting ON time behavior is
overconservative as a general operating design value for
two reasons. First, actual power supply application cir-
cuits present an inductive load to the V
SW
node. The
APPLICATIONS INFORMATION
WUU
U
resulting ramping current behavior helps overdrive the
current comparator (current mode switching) and reduce
its propagation delay, hastening output switch turnoff.
Second, and more importantly, actual power supply op-
eration involves a feedback amplifier that adjusts the V
C
node control voltage to maintain proper output voltage. As
progressively shorter ON times are required, the feedback
loop acts to reduce V
C
, and the resulting overdrive further
reduces the propagation delay in the current comparator.
A suggested worst-case limit for minimum switch ON time
in actual operation is 350ns.
A potential controllability problem arises if the LT1776 is
called upon to produce an ON time shorter than its ability.
Feedback loop action will lower then reduce the V
C
control
voltage to the point where some sort of cycle-skipping or
odd/even cycle behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and high f
OSC
can result in an unacceptably short
minimum switch ON time. Cycle skipping and/or odd/
even cycle behavior will result although correct output
voltage is usually maintained.
Minimum Load Considerations
As discussed previously, a lightly loaded LT1776 with V
C
pin control voltage below the boost threshold will operate
in low dV/dt mode. This affords greater controllability at
light loads, as minimum t
ON
requirements are relaxed.
However, some users may be indifferent to pulse skipping
behavior, but instead may be concerned with maintaining
maximum possible efficiency at light loads. This require-
ment can be satisfied by forcing the part into Burst Mode
TM
operation. The use of an external comparator whose
Burst Mode is a trademark of Linear Technology Corporation.
11
LT1776
APPLICATIONS INFORMATION
WUU
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output controls the shutdown pin allows high efficiency at
light loads through Burst Mode operation behavior (see
Typical Applications and Figure 8).
Maximum Load/Short-Circuit Considerations
The LT1776 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, V
C
, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by V
C
. However, there is finite response
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum ON time
t
ON(MIN)
. When combined with the large ratio of V
IN
to
(V
F
+ I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
ft
VIR
V
ON
F
IN
+
where:
f = switching frequency
t
ON
= switch ON time
V
F
= diode forward voltage
V
IN
= Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at I
PK
, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1776 clock frequency
of 200KHz, a V
IN
of 40V and a (V
F
+ I • R) of say 0.7V, the
maximum t
ON
to maintain control would be approximately
90ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscillator
when the FB pin voltage is abnormally low thereby indicat-
ing some sort of short-circuit condition. Figure 2 shows
the typical response of Oscillator Frequency vs FB divider
Thevenin voltage and impedance. Oscillator frequency is
unaffected until FB voltage drops to about 2/3 of its normal
value. Below this point the oscillator frequency decreases
roughly linearly down to a limit of about 30kHz. This lower
oscillator frequency during short-circuit conditions can
then maintain control with the effective minimum ON time.
A further potential problem with short-circuit operation
might occur if the user were operating the part with its
oscillator slaved to an external frequency source via the
SYNC pin. However, the LT1776 has circuitry that auto-
matically disables the sync function when the oscillator is
slowed down due to abnormally low FB voltage.
FB DIVIDER THEVENIN VOLTAGE (V)
0
f
OSC
(kHz)
0
50
100
150
200
0.25 0.50 0.75 1.00
1776 F02
1.25
R
TH
LT1776
FB
R
TH
= 22k
R
TH
= 10k
R
TH
= 4.7k
Figure 2. Oscillator Frequency vs FB Divider
Thevenin Voltage and Impedance
Feedback Divider Considerations
An LT1776 application typically includes a resistive divider
between V
OUT
and ground, the center node of which drives
the FB pin to the reference voltage V
REF
. This establishes
a fixed ratio between the two resistors, but a second
degree of freedom is offered by the overall impedance level
of the resistor pair. The most obvious effect this has is one
of efficiencya higher resistance feedback divider will
waste less power and offer somewhat higher efficiency,
especially at light load.
12
LT1776
APPLICATIONS INFORMATION
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P
AC
= 1/2 • V
IN
• I
OUT
• (t
r
+ t
f
+ 30ns) • f
t
r
= (V
IN
/1.6)ns in high dV/dt mode
(V
IN
/0.16)ns in low dV/dt mode
t
f
= (V
IN
/1.6)ns (irrespective of dV/dt mode)
f = switching frequency
Total power dissipation of the die is simply the sum of
quiescent, DC and AC losses previously calculated.
P
D(TOTAL)
= P
Q
+ P
DC
+ P
AC
Frequency Compensation
Loop frequency compensation is performed by connect-
ing a capacitor, or in most cases a series RC, from the
output of the error amplifier (V
C
pin) to ground. Proper
loop compensation may be obtained by empirical meth-
ods as described in detail in Application Note 19. Briefly,
this involves applying a load transient and observing the
dynamic response over the expected range of V
IN
and
I
LOAD
values.
As a practical matter, a second small capacitor, directly
from the V
C
pin to ground is generally recommended to
attenuate capacitive coupling from the V
SW
pin. A typical
value for this capacitor is 100pF. (See Switch Node Con-
siderations).
Switch Node Considerations
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power path. B field (magnetic) radiation is minimized by
keeping output diode, switch pin and input bypass capaci-
tor leads as short as possible. E field radiation is kept low
by minimizing the length and area of all traces connected
to the switch pin (V
SW
). A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
However, remember that oscillator slowdown to achieve
short-circuit protection (discussed above) is dependent
on FB pin behavior, and this in turn, is sensitive to FB node
external impedance. Figure 2 shows the typical relation-
ship between FB divider Thevenin voltage and impedance,
and oscillator frequency. This shows that as feedback
network impedance increases beyond 10k, complete os-
cillator slowdown is not achieved, and short-circuit pro-
tection may be compromised. And as a practical matter,
the product of FB pin bias current and larger FB network
impedances will cause increasing output voltage error.
(Nominal cancellation for 10k of FB Thevenin impedance
is included internally.)
Thermal Considerations
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110°C/W
for the 8-pin SO (S8) and 130°C/W for 8-pin PDIP (N8).
Quiescent power is given by:
P
Q
= I
IN
• V
IN
+ I
VCC
• V
OUT
(This assumes that the V
CC
pin is connected to V
OUT
.)
Power loss internal to the LT1776 related to actual output
current is composed of both DC and AC switching losses.
These can be roughly estimated as follows:
DC switching losses are dominated by output switch “ON
voltage”, i.e.,
P
DC
= V
ON
• I
OUT
• DC
V
ON
= Output switch ON voltage, typically 1V at 500mA
I
OUT
= Output current
DC = ON duty cycle
AC switching losses are typically dominated by power lost
due to the finite rise time and fall time at the V
SW
node.
Assuming, for simplicity, a linear ramp up of both voltage
and current and a current rise/fall time equal to 15ns,

LT1776CN8#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Wide In Rng, Hi Eff, Buck Sw Reg
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