Detailed Description
DC-DC Converter Control Architecture
The MAX8650 step-down controller uses a PWM, cur-
rent-mode control scheme. An internal transconduc-
tance amplifier establishes an integrated error voltage.
The heart of the PWM controller is an open-loop com-
parator that compares the integrated voltage-feedback
signal against the amplified current-sense signal plus
the adjustable slope-compensation ramp, which are
summed into the main PWM comparator to preserve
inner-loop stability. At each rising edge of the internal
clock, the high-side MOSFET turns on until the PWM
comparator trips or the maximum duty cycle is
reached. During this on-time, current ramps up through
the inductor, storing energy in a magnetic field and
sourcing current to the output. The current-mode feed-
back system regulates the peak inductor current as a
function of the output-voltage error signal. The circuit
acts as a switch-mode transconductance amplifier and
pushes the output LC filter pole normally found in a
voltage-mode PWM to a higher frequency.
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on.
The inductor releases the stored energy as the current
ramps down, providing current to the output. The output
capacitor stores charge when the inductor current
exceeds the required load current and discharges when
the inductor current is lower, smoothing the voltage
across the load. Under soft-overload conditions, when
the peak inductor current exceeds the selected current
limit (see the
Current-Limit Circuit
section), the high-side
MOSFET is turned off immediately and the low-side
MOSFET is turned on and remains on to let the inductor
current ramp down until the next clock cycle. Under
heavy-overload or short-circuit conditions, the valley
foldback current limit is enabled to reduce power dissi-
pation of external components.
The MAX8650 operates in a forced-PWM mode. As a
result, the controller maintains a constant switching fre-
quency, regardless of load, to allow for easier filtering
of the switching noise.
Internal Linear Regulators
The MAX8650 contains two internal LDO regulators. The
AVL regulator provides 5V for the IC’s internal circuitry,
and the VL regulator provides 6.5V for the MOSFET gate
drivers. Connect a 4.7µF ceramic capacitor from VL to
PGND, and connect a 1µF ceramic capacitor from AVL
to GND. For applications where the input voltage is
between 4.5V and 7V, connect VL directly to IN and con-
nect a 10Ω resistor from VL to AVL.
Undervoltage Lockout
When AVL drops below 4.03V, the MAX8650 assumes
that the supply voltage is too low for proper operation,
so the undervoltage-lockout (UVLO) circuitry inhibits
switching and forces the DL and DH gate drivers low.
When AVL rises above 4.15V, the controller enters the
startup sequence and then resumes normal operation.
Startup and Soft-Start
The internal soft-start circuitry gradually ramps up the
reference voltage to control the rate of rise of the step-
down controller’s output and reduce input surge cur-
rents during startup. The soft-start period is determined
by the value of the capacitor from SS to GND. The soft-
start time is approximately (30.4ms/µF) x C
SS
. The
MAX8650 also features monotonic output-voltage rise;
therefore, both external power MOSFETs are kept off if
the voltage at FB is higher than the voltage at SS. This
allows the MAX8650 to start up into a prebiased output
without pulling the output voltage down.
Before the MAX8650 can begin the soft-start and power-
up sequence, the following conditions must be met:
•V
AVL
exceeds the 4.15V UVLO threshold.
• EN is at logic-high.
• The thermal limit is not exceeded.
Enable (EN)
The MAX8650 features a low-power shutdown mode. A
logic-low at EN shuts down the controller. During shut-
down, the output is high impedance, and both DH and
DL are low. Shutdown reduces the quiescent current
(I
Q
) to less than 10µA. A logic-high at EN enables the
controller.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX8650 also uses the synchronous rectifier to ensure
proper startup of the boost gate-driver circuit and to
provide the current-limit signal. The low-side gate driver
(DL) swings from 0 to the 6.5V provided from VL. The
DL waveform is always the complement of the DH high-
side gate-drive waveform (with controlled dead time to
prevent cross-conduction or shoot-through). An adap-
tive dead-time circuit monitors the DL voltage and pre-
vents the high-side MOSFET from turning on until DL is
fully off. For the dead-time circuit to work properly,
there must be a low-resistance, low-inductance path
from the DL driver to the MOSFET gate. Otherwise,
the sense circuitry in the MAX8650 can interpret the
MOSFET gate as off when gate charge actually
remains. Use very short, wide traces, approximately 10
MAX8650
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
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