MC74HC390A
http://onsemi.com
4
TIMING REQUIREMENTS (Input t
r
= t
f
= 6 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v85_C v125_C
t
rec
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 3)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
t
w
Minimum Pulse Width, Clock A, Clock B
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
t
w
Minimum Pulse Width, Reset
(Figure 3)
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
ns
t
f
, t
f
Maximum Input Rise and Fall Times
(Figure 2)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip−flops, and forces Q
A
through Q
D
low.
OUTPUTS
Q
A
(Pins 3, 13)
Output of the ÷ 2 counter.
Q
B
, Q
C
, Q
D
(Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. Q
D
is the most significant bit.
Q
A
is the least significant bit when the counter is connected
for BCD output as in Figure 5. Q
B
is the least significant bit
when the counter is operating in the bi−quinary mode as in
Figure 6.
SWITCHING WAVEFORMS
Q
t
r
t
f
t
PLH
t
PHL
t
TLH
t
THL
V
CC
GND
CLOCK
10%
50%
90%
1/f
max
t
w
t
rec
RESET
Figure 2.
V
CC
GND
V
CC
GND
10%
50%
90%
Q
CLOCK
50%
50%
50%
t
PHL
t
w
10%
Figure 3.
