74FCT162827ATPVG8

4
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162827AT/CT
FAST CMOS 20-BIT BUFFER
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
ΔI
CC Quiescent Power Supply Current VCC = Max. 0.5 1.5 mA
TTL Inputs HIGH VIN = 3.4V
(3)
ICCD Dynamic Power Supply Current
(4)
VCC = Max. VIN = VCC 60 100 µ A /
Outputs Open VIN = GND MHz
xOE
1 = xOE2 = GND
One Input Toggling
50% Duty Cycle
I
C Total Power Supply Current
(6)
VCC = Max. VIN = VCC 0.6 1.5 mA
Outputs Open VIN = GND
fi = 10MHz
50% Duty Cycle V
IN = 3.4V 0.9 2.3
xOE1 = xOE2 = GND VIN = GND
One Bit Toggling
V
CC = Max. VIN = VCC 3 5.5
(5)
Outputs Open VIN = GND
fi = 2.5MHz
50% Duty Cycle V
IN = 3.4V 8 20.5
(5)
xOE1 = xOE2 = GND VIN = GND
Twenty Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
POWER SUPPLY CHARACTERISTICS
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IDT74FCT162827AT/CT
FAST CMOS 20-BIT BUFFER
INDUSTRIAL TEMPERATURE RANGE
FCT162827AT FCT162827CT
Symbol Parameter Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH Propagation Delay CL = 50pF 1.5 8 1.5 3.7 ns
tPHL xAx to xYx RL = 500Ω
C
L = 300pF
(4)
1.5 15 1.5 7
RL = 500Ω
tPZH Output Enable Time CL = 50pF 1.5 12 .5 4.8 ns
t
PZL xOEx to xYx RL = 500Ω
C
L = 300pF
(4)
1.5 23 1.5 9
RL = 500Ω
t
PHZ Output Disable Time CL = 5pF
(4)
1.5 9 1.5 4 ns
tPLZ xOEx to xYx RL = 500Ω
C
L = 50pF 1.5 10 1.5 4
RL = 500Ω
tSK(o) Output Skew
(3)
0.5 0.5 ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
6
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162827AT/CT
FAST CMOS 20-BIT BUFFER
Pulse
Generator
RT
D.U.T.
V
CC
V
IN
CL
V
OUT
50pF
500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
t
PLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
C
L = Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse Generator.

74FCT162827ATPVG8

Mfr. #:
Manufacturer:
IDT
Description:
Buffers & Line Drivers 16BIT BUF
Lifecycle:
New from this manufacturer.
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