10
FN9151.5
February 13, 2008
Pin Descriptions
VIN
This pin powers the controller and must be closely
decoupled to ground using a ceramic capacitor as close to
the VIN pin as possible.
SGND
This pin provides the signal and power ground for the IC. Tie
this pin to the ground plane through the lowest impedance
connection.
LGATE
This pin provides the PWM-controlled gate drive for the
lower MOSFET.
PHASE
This pin is the junction point of the output filter inductor, the
upper MOSFET source and the lower MOSFET drain. This
pin is used to monitor the voltage drop across the upper
MOSFET for overcurrent protection. This pin also provides a
return path for the upper gate drive.
UGATE
This pin provides the PWM-controlled gate drive for the
upper MOSFET.
BOOT
This pin powers the upper MOSFET driver. Connect this pin
to the junction of the bootstrap capacitor and the cathode of
the bootstrap diode. The anode of the bootstrap diode is
connected to the VCC5 pin.
FB
This pin is connected to the feedback resistor divider and
provides the voltage feedback signal for the controller. This
pin sets the output voltage of the converter.
COMP
This pin is the error amplifier output pin. It is used as the
compensation point for the PWM error amplifier.
PGOOD
This pin provides a power good status. It is an open collector
output used to indicate the status of the output voltage.
RT
This is the oscillator frequency selection pin. Connecting this
pin directly to VCC5 will select the oscillator free running
frequency of 300kHz. By placing a resistor from this pin to
GND, the oscillator frequency can be programmed from
100kHz to 1.4MHz. Figure 7 shows the oscillator frequency
vs. the RT resistance.
CDEL
The PGOOD signal can be delayed by a time proportional to
a CDEL current of 2µA and the value of the capacitor
connected between this pin and ground. A 0.1µF will
typically provide 125ms delay. When in the Voltage
Margining mode the CDEL current is 100µA typical and
provides the delay for the output voltage slew rate, 2.5ms
typical for the 0.1µF capacitor.
PGND
This pin provides the power ground for the IC. Tie this pin to
the ground plane through the lowest impedance connection.
PVCC
This pin is the power connection for the gate drivers.
Connect this pin to the VCC5 pin.
VCC5
This pin is the output of the internal 5V LDO. Connect a
minimum of 4.7µF ceramic decoupling capacitor as close to
the IC as possible at this pin. Refer to Table 1.
ENSS
This pin provides enable/disable function and soft-start for
the PWM output. The output drivers are turned off when this
pin is held below 1V.
OCSET
Connect a resistor (R
OCSET
) and a capacitor from this pin to
the drain of the upper MOSFET. R
OCSET
, an internal 100µA
current source (I
OCSET
), and the upper MOSFET on
resistance r
DS(ON)
set the converter overcurrent (OC) trip
point.
TABLE 1. INPUT SUPPLY CONFIGURATION
INPUT PIN CONFIGURATION
5.6V to 16V Connect the input to the VIN pin. The VCC5
pin will provide a 5V output from the internal
LDO. Connect PVCC to VCC5.
5V +±10% Connect the input to the VCC5 pin. Connect
the PVCC and VIN pins to VCC5.
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
0 25 50 75 100 125 150
RT (kΩ)
FREQUENCY (kHz)
FIGURE 7. OSCILLATOR FREQUENCY vs. RT
ISL6420
11
FN9151.5
February 13, 2008
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not connected
to VCC5 then this pin serves as GPIO1. Refer to Table 2 for
GPIO1 commands interpretation.
If VMSET/MODE is connected to VCC5 then this pin will
serve as REFIN. As REFIN, this pin is the non-inverting input
to the error amplifier. Connect the desired reference voltage
to this pin in the range of 0.6V to 1.25V.
Connect this pin to VCC5 to use internal reference.
REFOUT
It provides buffered reference output for REFIN. Connect
2.2µF decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to disable
voltage margining. When not tied to VCC5, this pin serves as
VMSET. Connect a resistor from this pin to ground to set the
delta for voltage margining. If voltage margining and external
reference tracking mode are not needed, this pin can be tied
directly to ground.
GPIO2
This is general purpose IO pin for voltage margining. Refer
to Table 2.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the
signal ground plane using at least five vias for a robust
thermal conduction path.
TABLE 2. VOLTAGE MARGINING CONTROLLED BY
GPIO1/REFIN AND GPIO2
GPIO1/REFIN GPIO2 VOUT
L L No Change
LH+ Delta VOUT
H L - Delta VOUT
H H Ignored
TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
FUNCTION/MODES
PIN CONFIGURATIONS
VMSET/MODE REFOUT GPIO1/REFIN GPIO2
Enable Voltage Margining Pin Connected to GND with
resistor. It is used as VMSET.
Connect a 2.2µF capacitor for
bypass of external reference.
Serves as a general
purpose I/O. Refer to
Table 2
Serves as a general
purpose I/O. Refer to
Table 2
No Voltage Margining.
Normal operation with
internal reference.
Buffered V
REFOUT
= 0.6V.
H Connect a 2.2µF capacitor to
GND.
H (Note 9) L
No Voltage Margining.
External reference.
Buffered V
REFOUT
=
V
REFIN
H Connect a 2.2µF capacitor to
GND.
Connect to an external
reference voltage source
(0.6V to 1.25V)
L
NOTES:
8. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
9. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
ISL6420
12
FN9151.5
February 13, 2008
Functional Description
Initialization
The ISL6420 automatically initializes upon receipt of power.
The Power-On Reset (POR) function monitors the internal
bias voltage generated from LDO output (VCC5) and the
ENSS pin. The POR function initiates the soft-start operation
after the VCC5 exceeds the POR threshold. The POR
function inhibits operation with the chip disabled (ENSS
pin <1V).
The device can operate from an input supply voltage of 5.6V
to 16V connected directly to the VIN pin using the internal 5V
linear regulator to bias the chip and supply the gate drivers.
For 5V ±10% applications, connect VIN to VCC5 to bypass
the linear regulator.
Soft-Start/Enable
The ISL6420 soft-start function uses an internal current
source and an external capacitor to reduce stresses and
surge current during startup.
When the output of the internal linear regulator reaches the
POR threshold, the POR function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor on the ENSS pin linearly from 0V to 3.3V.
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the dv/dt
of the ENSS voltage. As the soft-start pin charges from 1V to
1.6V, the reference voltage charges from 0V to 0.6V.
Figure 8 shows a typical soft-start sequence.
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r
DS(ON)
to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor connected
to the drain of the upper FET and the OCSET pin programs
the overcurrent trip level. The PHASE node voltage will be
compared against the voltage on the OCSET pin, while the
upper FET is on. A current (100µA typically) is pulled from
the OCSET pin to establish the OCSET voltage. If PHASE is
lower than OCSET while the upper FET is on then an over-
current condition is detected for that clock cycle. The upper
gate pulse is immediately terminated, and a counter is incre-
mented. If an overcurrent condition is detected for
8 consecutive clock cycles, and the circuit is not in soft-start,
the ISL6420 enters into the soft-start hiccup mode. During
hiccup, the external capacitor on the ENSS pin is dis-
charged. After the capacitor is discharged, it is released and
a soft-start cycle is initiated. There are three dummy soft-
start delay cycles to allow the MOSFETs to cool down, to
keep the average power dissipation in hiccup mode at an
acceptable level. At the forth soft-start cycle, the output
starts a normal soft-start cycle, and the output tries to ramp.
During soft-start, pulse termination current limiting is
enabled, but the 8-cycle hiccup counter is held in reset until
soft-start is completed. Figure 9 shows the overcurrent hic-
cup mode.
The overcurrent function will trip at a peak inductor current
(I
OC
) determined from Equation 1, where I
OCSET
is the
internal OCSET current source.
The OC trip point varies mainly due to the upper MOSFETs
r
DS(ON)
variations. To avoid overcurrent tripping in the
normal operating load range, find the R
OCSET
resistor from
the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. Determine ,
where ΔI is the output inductor ripple current.
FIGURE 8. TYPICAL SOFT-START WAVEFORM
FIGURE 9. TYPICAL OVER-CURRENT HICCUP MODE
VOUT
IOUT
PHASE
ENSS
I
OC
I
OCSET
R
OCSET
R
DS ON()
---------------------------------------------------
=
(EQ. 1)
I
OC
for I
OC
I
OUT MAX()
ΔI()2+>
ISL6420

ISL6420IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers SYNCH BUCK PWM CONT W/4 5V-16V INPUT20LD
Lifecycle:
New from this manufacturer.
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