4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM 16 REVISION E 04/28/16
9DBV0441 DATASHEET
Revision History
Rev. Initiator Issue Date Description Page #
A RDW 8/13/2012
1. Removed "Differential" from DS title and Recommended Application,
corrected typo's in Description. Updated block diagram to indicate
internal terminations.
2. Corrected spelling error in pullup/pulldown text under pinout
3. Updated all electrical tables and added "Industry Limit" column to
"Phase Jitter Parameters".
4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6]
definition.
5. Added thermal data to page 12.
6. Added NLG32 to "Package Outline and Package Dimensions" on page
13.
7. Move to final.
1,2,5-
8,10,
12,13
B RDW 2/25/2013
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
6
C RDW 10/27/2014
1. Updated front page text for consistency and updated block diagram
resistor colors to highlight internal resistors.
2. Updated max frequency of 100MHz PLL mode from 110MHz to
140MHz
3. Updated max frequency of 125MHz PLL mode from 137.5MHz to
175MHz
4. Updated max frequency of 50MHz PLL mode from 55MHz to 65MHz
1,6
D RDW 11/26/2014
1. Updated Key Specifications with addtive phase jitter.
2. Added additive phase jitter plot to specifications.
1, 9-10
E RDW 4/22/2016
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
7
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9DBV0441AKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1.8V 4 O/P PCIE GEN1-2-3 ZDB/BUFFER
Lifecycle:
New from this manufacturer.
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