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9DBV0441AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REVISION E 04/28/16 7 4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
9DBV0441 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
1.8V Supply Voltage VDD
Supply voltage for core, analog and LVCMOS
outputs
1.7 1.8 1.9 V 1
T
COM
Commmercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V 1
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V1
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
Bypass mode 1 200 MHz 2
F
i
p
ll100
100MHz PLL mode 50 100.00 140 MHz 2
F
i
p
ll125
125MHz PLL mode 62.5 125.00 175 MHz 2
F
i
p
ll62
50MHz PLL mode 25 50.00 65 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,6
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6 1 ms 1,2
Input SS Modulation
Frequency
f
MODI N
Allowable Frequency
(Triangular Modulation)
30 31.500 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.8 V 1, 4
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 1, 5
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
1.7 3.6 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 1,7
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
6
DIF_IN input
7
The differential input clock must be running for the SMBus to be active
4
For V
DDSMB
< 3.3V, V
ILSMB
<= 0.35V
DDSMB
5
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.65V
DDSMB
Ambient Operating
Temperature
Input Current
Input Frequency
Capacitance
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM 8 REVISION E 04/28/16
9DBV0441 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on 3.0V/ns settin
g
1.1 2 3
V/ns
1, 2, 3
Scope averaging on 2.0V/ns setting 1.9 3 4
V/ns
1, 2, 3
Slew rate matchin
g
Δ
Trf Slew rate matchin
g
, Scope avera
g
in
g
on 7 20
%
1, 2, 4
Voltage High V
HIGH
660 774 850 1,7
Voltage Low V
LOW
-150 18 150 1,7
Max Voltage Vmax 821 1150 1
Min Volta
g
eVmin -300-15 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1536 mV 1,2,7
Crossin
g
Volta
g
e (abs) Vcross_abs Scope avera
g
in
g
off 250 414 550 mV 1,5,7
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 13 140 mV 1, 6
2
Measured from differential waveform
Slew rate Trf
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
∆
-
Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDAOP
VDDA+VDDR, PLL Mode, @100MHz 11 15 mA 1
I
DDOP
VDD1.8, All outputs active @100MHz 25 35 mA 1
I
DDAPD
VDDA+VDDR, PLL Mode, @100MHz 1 mA 1,2
I
DDPD
VDD1.8, Outputs Low/Low 1.2 mA 1, 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input clock stopped.
Operating Supply Current
Powerdown Current
REVISION E 04/28/16 9 4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
9DBV0441 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode 2 2.7 4 MHz 1,5
-3dB point in Low BW Mode 1 1.4 2 MHz 1,5
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1.2 2 dB 1
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode @100MHz -1 0 1 % 1,3
t
p
dBYP
Bypass Mode, V
T
= 50% 3000 3600 4500 ps 1
t
p
dPLL
PLL Mode V
T
= 50% 0 92 200 ps 1,4
Skew, Output to Output t
sk3
V
T
= 50% 28 50 ps 1,4
PLL mode 16 50 ps 1,2
Additive Jitter in Bypass Mode 0.1 25 ps 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
PLL Bandwidth BW
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
INDUSTRY
LIMIT UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 34 52 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 1.4 3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.2
2.5 3.1
ps
(rms)
1,2
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
0.6 1
ps
(rms)
1,2,4
t
jphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9 2 NA
ps
(rms)
1,6
t
jphPCIeG1
PCIe Gen 1 0.6 5 N/A ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.3 N/A
ps
(rms)
1,2,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.05 0.1 N/A
ps
(rms)
1,2,5
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.05 0.1 N/A
ps
(rms)
1,2,4,
5
t
jphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165 200 N/A
fs
(rms)
1,6
t
jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251 300 N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
4
For RMS fi
g
ures, additive jitter is calculated by solvin
g
the followin
g
equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGV0831 or equivalent
6
Driven by Rohde&Schwarz SMA100
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Phase Jitter, PLL Mode
t
jphPCIeG2
Additive Phase Jitter,
Bypass Mode
t
jphPCIeG2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DBV0441AKILFT

Mfr. #:
Buy 9DBV0441AKILFT
Manufacturer:
IDT
Description:
Clock Buffer 1.8V 4 O/P PCIE GEN1-2-3 ZDB/BUFFER
Lifecycle:
New from this manufacturer.
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