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854S058AGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ICS854S058AGI REVISION A OCTOBER 29, 2012 1 ©2012 Integrated Device Technology, Inc.
DATASHEET
8:1 Differential-to-LVDS Clock Multiplexer ICS854S058I
General Description
The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S058I has 8
selectable differential clock inputs. The PCLK, nPCLK input pairs
can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Features
• High speed 8:1 differential multiplexer
• One differential LVDS output pair
• Eight selectable differential PCLK, nPCLK input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, SSTL, CML
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
• Additive phase jitter, RMS: 0.065ps (typical)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 600ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packaging
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK7
nPCLK7
nPCLK6
PCLK6
Q
V
DD
nQ
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
SEL2
SEL1
SEL0
Pulldown
Pulldown
Pulldown
Q
nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PCLK2
nPCLK2
PCLK3
nPCLK3
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
PCLK4
nPCLK4
PCLK5
nPCLK5
PCLK6
nPCLK6
PCLK7
nPCLK7
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
(default)
Pin Assignment
ICS854S058I
24-Lead TSSOP, 173-MIL
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
Block Diagram
ICS854S058I Datasheet 8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
ICS854S058AGI REVISION A OCTOBER 29, 2012 2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
2 nPCLK0 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
3 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
4 nPCLK1 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
5, 20 V
DD
Power Positive supply pins.
6, 7, 8
SEL0,
SEL1,
SEL2
Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels.
9 PCLK2 Input Pulldown Non-inverting differential LVPECL clock input.
10 nPCLK2 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
11 PCLK3 Input Pulldown Non-inverting differential LVPECL clock input.
12 nPCLK3 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
13 nPCLK4 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
14 PCLK4 Input Pulldown Non-inverting differential LVPECL clock input.
15 nPCLK5 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
16 PCLK5 Input Pulldown Non-inverting differential LVPECL clock input.
17 GND Power Power supply ground.
18, 19 nQ, Q Output Differential output pair. LVDS interface levels.
21 nPCLK6 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
22 PCLK6 Input Pulldown Non-inverting differential LVPECL clock input.
23 nPCLK7 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
24 PCLK7 Input Pulldown Non-inverting differential LVPECL clock input.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Pulldown Resistor 75 k
R
VDD
/2 RPullup/Pulldown Resistor 50 k
ICS854S058I Datasheet 8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
ICS854S058AGI REVISION A OCTOBER 29, 2012 3 ©2012 Integrated Device Technology, Inc.
Table 3. Clock Input Function Table
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Inputs Outputs
SEL2 SEL1 SEL0 Q nQ
0 (default) 0 0 PCLK0 nPCLK0
0 0 1 PCLK1 nPCLK1
0 1 0 PCLK2 nPCLK2
0 1 1 PCLK3 nPCLK3
1 0 0 PCLK4 nPCLK4
1 0 1 PCLK5 nPCLK5
1 1 0 PCLK6 nPCLK6
1 1 1 PCLK7 nPCLK7
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance,
JA
85.1°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 66 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

854S058AGILFT

Mfr. #:
Buy 854S058AGILFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX
Lifecycle:
New from this manufacturer.
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