KAI−2093
www.onsemi.com
13
Connections to the Image Sensor
The reset clock signal operates at the pixel frequency. The
traces on the circuit board to the reset clock pins should be
kept short and of equal length to ensure that the reset pulse
arrives at each pin simultaneously. The circuit board traces
to the horizontal clock pins should also be placed to ensure
that the clock edges arrive at each pin simultaneously. If
reset pulses and the horizontal clock edges are misaligned
the noise performance of the sensor will be degraded and
balancing the offset and gain of the two output amplifiers
will be difficult.
The bias voltages on OG, RD, VSS and VDD should be
well filtered with capacitors placed as close to the pins as
possible. Noise on the video outputs will be most strongly
affected by noise on VSS, VDD, GND, and VSUB. If the
electronic shutter is not used then a filtering capacitor should
also be placed on VSUB. If the electronic shutter is used, the
VSUB voltage should be kept as clean and noise free as
possible.
The voltage on VSS may be set by using the 0.6 to 0.7 volt
drop across a diode. Place the diode from VSS to GND. To
disable one of the output amplifiers connect VDD to GND,
do not let VDD float.
The ESD voltage must reach its operating point before any
of the horizontal clocks reach their low level. If any pin on
the sensor comes within 1 V of the ESD pin the electrostatic
damage protection circuit will become active and will not
turn off until all voltages are powered down. Operating the
sensor with the ESD protection circuit active may damage
the sensor.
