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NLV74HC164ADR2G

P1-P3P4-P6P7-P9P10-P11
MC74HC164A
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test ConditionsParameterSymbol Unit
v 125_Cv 85_C
−55_C to
25_C
V
CC
V
Test ConditionsParameterSymbol
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol Parameter
V
CC
V
Guaranteed Limit
Unit
−55_C to
25_C
v 85_C v 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
20
40
50
10
20
35
45
10
20
30
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
160
100
32
27
200
150
40
34
250
200
48
42
ns
t
PHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
175
100
35
30
220
150
44
37
260
200
53
45
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance — 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
180
MC74HC164A
http://onsemi.com
5
TIMING REQUIREMENTS (Input t
r
= t
f
= 6 ns)
Symbol Parameter
V
CC
V
Guaranteed Limit
Unit
−55_C to
25_C
v 85_C v 125_C
t
su
Minimum Setup Time, A1 or A2 to Clock
(Figure 3)
2.0
3.0
4.5
6.0
25
15
7
5
35
20
8
6
40
25
9
6
ns
t
h
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC164A
http://onsemi.com
6
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a data−enable input. When only one serial input is
used, the other must be connected to V
CC
.
Clock (Pin 8)
Shift Register Clock. A positive−going transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
Q
A
− Q
H
(Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active−Low, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flip−flops and sets
Outputs Q
A
− Q
H
to the low level state.
SWITCHING WAVEFORMS
t
f
V
CC
GND
90%
50%
10%
t
w
t
PLH
t
PHL
CLOCK
Q
t
TLH
t
THL
Figure 1.
RESET
t
rec
Figure 2.
t
r
1/f
max
90%
50%
10%
V
CC
GND
V
CC
GND
Q
CLOCK 50%
50%
50%
t
PHL
t
w
A1 OR A2
Figure 3.
V
CC
GND
V
CC
GND
50%
50%
CLOCK
t
su
t
h
VALID
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
P1-P3P4-P6P7-P9P10-P11

NLV74HC164ADR2G

Mfr. #:
Buy NLV74HC164ADR2G
Manufacturer:
ON Semiconductor
Description:
Serial to Parallel Logic Converters 8-BIT SERIAL-INPUT/PARALL
Lifecycle:
New from this manufacturer.
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