19
LTC3830/LTC3830-1
3830fa
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V
CC
, PV
CC1
and PV
CC2
decoupling capacitors should
be as close to the LTC3830 as possible. The 4.7µF and 1µF
bypass capacitors shown at V
CC
, PV
CC1
and PV
CC2
will help
provide optimum regulation performance.
5. The (+) plate of C
IN
should be connected as close as
possible to the drain of the upper MOSFET, Q1. An addi-
tional 1µF ceramic capacitor between V
IN
and power ground
is recommended.
6. The SENSE and V
FB
pins are very sensitive to pickup from
the switching node. Care should be taken to isolate SENSE
and V
FB
from possible capacitive coupling to the inductor
switching signal. Connecting the SENSE
+
and SENSE
–
close
to the load can significantly improve load regulation.
7. Kelvin sense I
MAX
and I
FB
at Q1’s drain and source pins.
PV
CC1
G1
I
MAX
I
FB
SENSE
+
G2
FB
SENSE
–
FREQSET
SHDN
COMP
SS
V
CC
LTC3830
PV
CC2
GND PGND
+
+
1µF
GND
GND
NC
100Ω
1k
V
IN
Q1A
Q2
PGND
Q1B
C
IN
+
C
OUT
3830 F11
V
OUT
L
O
C
SS
C1
C
C
4.7µF
NC
R
C
1µF
0.1µF
PGND
PV
CC
Figure 11. Typical Schematic Showing Layout Considerations
APPLICATIO S I FOR ATIO
WUUU
