527R-01ILF Datasheet 527R-01ILFT, 527R-01ILF, 527R-01LF | P4-P6

ICS527-01

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 4

ICS527-01 REV G 051310

because of internal pull-ups) during Printed Circuit

Board layout, so the ICS527-01 automatically produces

the correct clock when all components are soldered. It

is also possible to connect the inputs to parallel I/O

ports in order to switch frequencies.

The output of the ICS527-01 can be determined by the

following simple equation:

Where:

Reference Divider Word (RDW) = 0 to 127

Feedback Divider Word (FDW) = 0 to 127

FB Frequency is the same as either CLK1 or

CLK2 depending on feedback connection

Also, the following operating ranges should be

observed:

S1 and S0 should be set for the frequency of CLK1,

according to the Frequency Range Table on page 2.

The device can be operated below the lower limits

stated in table 2, however, jitter and skew may be

higher. Therefore, if your expected output frequency

covers more than one frequency range, use the

setting for the highest frequency expected.

The dividers are expressed as integers. For example, if

a 50 MHz output on CLK1 is desired from a 40 MHz

input, the reference divider word (RDW) should be 2

and the feedback divider word (FDW) should be 3 which

gives the required 5/4 multiplication. Then R6:R0 is

0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this

example assumes CLK1 is connected to FBIN.S1:S0 is

set by referring to the Frequency Range Table. The

setting for 50 MHz is 00.

For assistance with configuring the device, please send

a description of your requirements using the “Technical

Support” link at www.idt.com.

FB Frequency Input Frequency

FDW 2+

RDW 2+

------------------------

×=

300kHz

Input Frequency

RDW 2+

-------------------------------------------

ICS527-01

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 5

ICS527-01 REV G 051310

Typical Example

The following connection diagram shows the implementation of the example from the previous section.

This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x

output drive is selected.T

Note: The series termination resistor is located before the feedback trace.

This will give the following waveforms:

Multiple Output Example

In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies

of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the

MK74CB218 which has dual 1 to 8 buffers with low pin-to-pin skew.

ICLK

GND

OECLK2

2XDRIVE

CLK1

CLK2

GND

VDD

DIV2

FBIN

PDTS

50 MHz

SYNC

0.01 F

40 MHz

0.01 F

VDD

40 MHz

ICLK

50 MHz

CLK1

SYNC

CLK2

ICS527-01

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 6

ICS527-01 REV G 051310

Using the equation for selecting dividers gives:

If FDW = 0, then RDW = 8. This gives the required divide-by-5 function. Setting pin DIV2 = 1 gives both a

25 MHz and a 50 MHz output from the ICS527-01. The FBIN pin is connected to the QA7 output of the

MK74CB218. This aligns all the outputs of the MK74CB218 with the 25 MHz input since the ICS527-01

aligns rising edges on the ICLK and FBIN pins. The propagation delay of the buffer is compensated by the

PLL.

In this example, series termination resistors have been omitted for clarity but should be used on all clock

outputs.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No via’s should be used

125 MHz,

ICLK

25 MHz,

QA0-7

50 MHz,

QB0-7

ICLK

GND

OECLK2

2XDRIVE

CLK1

CLK2

GND

VDD

DIV2

FBIN

PDTS

0.01 F

125 MHz

25 MHz

0.01 F

VDD

QB5

QA3

QB6

QB7

VDD

GND

QA5

QA6

QA7

QB3

QB4

GND

VDD

QA1

QA2

QB1

QB2

INA

QA0

INB

QB0

QA4

GND

0.01 F

MK74CB218

ICS527-01

The layout design above produces the waveforms shown below.

Note: Series terminating resistors are not shown.

0.01 F

(FDW + 2)

(RDW + 2)

25 MHz = 125 MHz x

P1-P3 P4-P6 P7-P9 P10-P11

527R-01ILF

Mfr. #:

Buy 527R-01ILF

Manufacturer:

IDT

Description:

Clock Buffer CLOCK SLICER CONFIGURABLE BUFFER

Lifecycle:

New from this manufacturer.

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527R-01ILF

527R-01ILF

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