ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 7
ICS527-01 REV G 051310
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock outputs.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS527-01. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS527-01. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature (Commercial) 0 to +70° C
Ambient Operating Temperature (Industrial) -40 to +85° C
Storage Temperature -65 to +150° C
Junction Temperature 125° C
Soldering Temperature 260° C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature, ICS527R-01 0 +70 ° C
Ambient Operating Temperature, ICS527R-01I -40 +85 ° C
Power Supply Voltage (measured in respect to GND) 3 3.3 3.6 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3 3.3 3.6 V
Supply Current IDD 15 MHz in, 60MHz out,
no load
8mA
Supply Current, Power Down IDDPD PDTS
=0 20 μA
Input High Voltage V
IH
2V
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 8
ICS527-01 REV G 051310
Input Low Voltage V
IL
0.8 V
Input High Voltage, ICLK and
FBIN
V
IH
Pins 7 and 8
VDD/2+1
V
Input Low Voltage, ICLK and
FBIN
V
IL
Pins 7 and 8
VDD/2-1
V
Output High Voltage V
OH
2XDRIVE = 0,
I
OH
= -12 mA
2.4 V
Output Low Voltage V
OL
2XDRIVE = 0,
I
OL
= 12 mA
0.4 V
Output High Voltage V
OH
2XDRIVE = 1,
I
OH
= -25 mA
2.4 V
Output Low Voltage V
OL
2XDRIVE = 1,
I
OL
= 25 mA
0.4 V
Short Circuit Current I
OS
2XDRIVE = 0,
CLK outputs
±70 mA
Short Circuit Current I
OS
2XDRIVE = 1,
CLK outputs
±140 mA
On-chip Pull-up Resistor R
PU
270 kΩ
Parameter Symbol Conditions Min. Typ. Max. Units
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 9
ICS527-01 REV G 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
External Components
The ICS527-01 requires two 0.01 µF decoupling capacitors to be connected between VDD and GND, one
on each side of the chip. They must be connected close to the device to minimize lead inductance. No
external power supply filtering is required for this device. A 33Ω series terminating resistor should be used
on the CLK1 and CLK2 output pins.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency F
IN
0.6 200 MHz
Output Frequency, CLK1 F
OUT
0 to +70° C4160MHz
-40 to +85° C4140MHz
CLK1 Frequency for Correct
SYNC Operation
66 MHz
Output Rise Time t
OR
0.8 to 2.0 V 1 ns
Output Fall Time t
OF
2.0 to 0.8 V 1 ns
Output Clock Duty Cycle t
OD
Measured at VDD/2,
C
L
=15 pF
45 50 55 %
Power Down Time, PDTS
low to
clocks tri-stated
50 ns
Power Up Time, PDTS
high to
clocks stable
10 ms
Absolute Clock Period Jitter t
ja
Deviation from mean ± 90 ps
One sigma Clock Period Jitter t
js
40 ps
Skew of Output Clocks t
IO
CLK1 to CLK2, Note 1 -250 250 ps
Input Capacitance C
IN
4pF
Input to Output Skew t
IO
ICLK to FBIN, Note 1 -250 250 ps
Device to Device Skew t
pi
Common ICLK, at FBIN 0 500 ps

527R-01ILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer CLOCK SLICER CONFIGURABLE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet