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SI91872DMP-50-E3

P1-P3P4-P6P7-P9P10-P10
Available
Si91872
Vishay Siliconix
Document Number: 72013
S-51147—Rev. F, 20-Jun-05
www.vishay.com
1
300-mA Low-Noise LDO Regulator
With Error Flag and Discharge Option
FEATURES
D Ultra Low Dropout—300 mV at 300-mA Load
D Low Noise—75 mV
RMS
(10-Hz to 100-kHz)
D Out-of-Regulation Error Flag (power good)
D Shutdown Control
D 130-mA Ground Current at 300-mA Load
D Fast Start-Up (50 mS)
D 1.5% Guaranteed Output Voltage Accuracy
D 400-mA Peak Output Current Capability
D Uses Low ESR Ceramic Capacitors
D Fast Line and Load Transient Response (v 30 ms)
D 1-mA Maximum Shutdown Current
D Output Current Limit
D Reverse Battery Protection
D Built-in Short Circuit and Thermal Protection
D Output—Auto-Discharge In Shutdown Mode
D Fixed 1.2, 1.8, 2.5, 2.6, 2.8, 3.0, 3.3, 5.0-V Output
Voltage Options
D MLP33-5 PowerPAKr Package
APPLICATIONS
D Cellular Phones, Wireless Handsets
D Noise-Sensitive Electronic Systems, Laptop and
Palmtop Computers
D PDAs
D Pagers
D Digital Cameras
D MP3 Player
D Wireless Modem
DESCRIPTION
The Si91872 is a 300-mA CMOS LDO (low dropout) voltage
regulator. It is the perfect choice for low voltage, low power
applications. An ultra low ground current and ultra fast turn-on
make this part attractive for battery operated power systems.
The Si91872 also offers ultra low dropout voltage to prolong
battery life in portable electronics. Systems requiring a quiet
voltage source will benefit from the Si91872’s low output noise.
The Si91872 is designed to maintain regulation while
delivering 400-mA peak current, making it ideal for systems
that have a high surge current upon turn-on.
For better transient response and regulation, an active
pull-down circuit is built into the Si91872 to clamp the output
voltage when it rises beyond normal regulation. The Si91872
automatically discharges the output voltage by connecting the
output to ground through a 100-W n-channel MOSFET when
the device is put in shutdown mode.
The Si91872 features reverse battery protection to limit
reverse current flow to approximately 1-mA in the event
reversed battery is applied at the input, thus preventing
damage to the IC.
The Si91872 is available in both the standard and
lead (Pb)-free 5-pin MLP33 PowerPAK packages and is
specified to operate over the industrial temperature range of
−40_C to 85_.
TYPICAL APPLICATION CIRCUIT
Si91872
V
IN
GND
SD
V
OUT
ERROR
V
IN
SD
V
OUT
2.2 mF
51 kW
ERROR
MLP33-5
2.2 mF
Si91872
Vishay Siliconix
www.vishay.com
2
Document Number: 72013
S-51147—Rev. F, 20-Jun-05
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
Input Voltage, V
IN
to GND −6.0 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
ERROR
, V
SD
(See Detailed Description) −0.3 V to V
IN
. . . . . . . . . . . . . . . . . .
Output Current, I
OUT
Short Circuit Protected. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage, V
OUT
−0.3 V to V
IN
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Power Dissipation, (P
d
)
b
2.3 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance (q
JA
)
a
55_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R
(
q
JA)
a
8_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature, T
J(max)
150_C. . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature, T
STG
−65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 20 mW/_C above T
A
= 25_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage, V
IN
2 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage, V
SD
0 V to V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current 0 to 300 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
IN
, C
OUT
a
(Ceramic) 2.2 mF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Ambient Temperature, T
A
−40_C to 85_C. . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature, T
J
−40_C to 125_C. . . . . . . . . . . . . . . . . . .
Notes
a. Maximum ESR of C
OUT:
0.2 W.
SPECIFICATIONS
Test Conditions Unless Specified
T
A
= 25_C
,
V
IN
= V
OUT(nom)
+ 1 V
,
I
OUT
= 1 mA
,
Limits
−40 to 85_C
Parameter Symbol
T
A
=
25_C
,
V
IN
=
V
OUT(nom)
+ 1 V
,
I
OUT
=
1 mA
,
C
IN
= 2 mF, C
OUT
= 2.0 mF, V
SD
= 1.5 V
Temp
a
Min
b
Typ
c
Max
b
Unit
Input Voltage Range V
IN
Full 2 6 V
V
OUT
w 18 V
Room −2.0 1 2.0
Output Voltage Accuracy
1 mA v I
OUT
v 300 mA
V
OUT
w 1.8 V
Full −3.0 1 3.0
%
Output Voltage Accuracy 1 mA v I
OUT
v 300 mA
V
OUT
= 1 2 V 1 5 V
Room −2.5 1 2.5
%
V
OUT
= 1.2 V, 1.5 V
Full −3.5 1 3.5
Line Regulation (V
OUT
v 3 V) Full −0.06 0.18
Line Regulation
(3.0 V < V
OUT
v3.6 V)
DV
OUT
100
DV
IN
V
OUT(nom)
From V
IN
= V
OUT(nom)
+ 1 V to V
OUT(nom)
+ 2 V
Full 0 0.3
%/V
Line Regulation (5-V Version)
()
From V
IN
= 5.5 V to 6 V Full 0 0.4
I
OUT
= 1 mA Room 1
Dt Vlt
dg
I
OUT
= 50 mA
Room 45 80
Dropout Voltage
d,
g
(V
OUT(nom)
w 2.6 V)
I
OUT
= 50 mA
Full 50 90
(V
OUT(nom)
w 2
.
6 V)
I
OUT
= 300 mA
Room 300 350
V
IN
− V
OUT
I
OUT
= 300 mA
Full 415
mV
V
IN
V
OUT
I
OUT
= 50 mA
Room 65 100
mV
Dro
p
out Volta
g
e
d,
g
I
OUT
= 50 mA
Full 120
Dropout Voltage
d,
g
(V
OUT(nom)
t 2.6 V, V
IN
w 2 V)
I
OUT
= 300 mA
Room 400 520
()
I
OUT
= 300 mA
Full 570
I
OUT
= 0 mA
Room 100 150
Ground Pin Current
e,
g
I
OUT
= 0 mA
Full 180
Ground Pin Current
e,
g
(V
OUT(nom)
v 3 V)
I
OUT
= 300 mA
Room 130 200
()
I
GND
I
OUT
= 300 mA
Full 330
mA
I
GND
I
OUT
= 0 mA
Room 110 170
mA
Ground Pin Current
e,
g
I
OUT
= 0 mA
Full 200
Ground Pin Current
e,
g
(V
OUT(nom)
u 3 V)
I
OUT
= 300 mA
Room 150 225
()
I
OUT
= 300 mA
Full 275
Peak Output current I
O(peak)
V
OUT
w 0.95 x V
OUT(nom)
. t
PW
= 2 ms Full 400 mA
Output Noise Voltage e
N
V
OUT
= 2.6 V, BW = 10 Hz to 100 kHz,
0 mA t I
OUT
t 150 mA
Room 75 mV(rms)
Si91872
Vishay Siliconix
Document Number: 72013
S-51147—Rev. F, 20-Jun-05
www.vishay.com
3
SPECIFICATIONS
Limits
−40 to 85_C
Temp
a
Test Conditions Unless Specified
T
A
= 25_C, V
IN
= V
OUT(nom)
+ 1 V, I
OUT
= 1 mA,
C
IN
= 2 mF, C
OUT
= 2.0 mF, V
SD
= 1.5 V
Parameter UnitMax
b
Typ
c
Min
b
Temp
a
Test Conditions Unless Specified
T
A
= 25_C, V
IN
= V
OUT(nom)
+ 1 V, I
OUT
= 1 mA,
C
IN
= 2 mF, C
OUT
= 2.0 mF, V
SD
= 1.5 V
Symbol
f = 1 kHz Room 60
Ripple Rejection DV
OUT
/DV
IN
I
OUT
= 300 mA f = 10 kHz Room 40 dB
pp j
OUT IN
OUT
f = 100 kHz Room 30
Dynamic Line Regulation DV
O(line)
V
IN
: V
OUT(nom)
+ 1 V to V
OUT(nom)
+ 2 V
t
r
/t
f
= 2 ms, I
OUT
= 300 mA
Room 20
mV
Dynamic Load Regulation DV
O(load)
I
OUT
: 1 mA to 300 mA, t
r
/t
f
= 2 ms Room 25
mV
Thermal Shutdown Junction
Temperature
T
J(S/D)
Room 150
_C
Thermal Hysteresis T
HYST
Room 20
C
Reverse current I
R
V
IN
= −6.0 V Room 1 mA
Short Circuit Current I
SC
V
OUT
= 0 V Room 700 mA
Shutdown
Shutdown Supply Current I
CC(off)
V
SD
= 0 V Room 0.1 1 mA
SD Pin Input Voltage
V
SD
High = Regulator ON (Rising) Full 1.5 V
IN
V
SD Pin Input Voltage V
SD
Low = Regulator OFF (Falling) Full 0.4
V
Auto Discharge Resistance R_DIS Si91872 Only Room 100 W
SD Pin Input Current
f
I
IN(SD)
V
SD
= 1.5 V, V
IN
= 6 V Room 0.7 mA
SD Hysteresis V
HYST(SD)
Full 150 mV
V
OUT
Turn-On Time t
ON
V
SD
(See Figure 1), I
LOAD
= 100 mA Room 50 ms
ERROR Output
ERROR High Leakage I
OFF
ERROR v V
IN
. V
OUT
in Regulation Full 1 mA
ERROR Low Voltage V
OL
I
SINK
= 0.5 mA Full 0.4 V
ERROR Volta
g
e Threshold V
ERR
O
R
V
OUT
Below V
OUT(nom)
g
, V
IN
w 2 V
V
OUT
Falling, I
OUT
= 1 mA, V
OUT(nom)
w 2 V
Full −2 −4 −6
ERROR Voltage Threshold
V
ERROR
V
OUT(nom)
g
t 2 V, V
IN
u 2 V Full −4
%
ERROR Voltage Threshold
Hysteresis
V
HYST(ERROR)
Room 1.5
%
Notes
a. Room = 25_C, Full = −40 to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V
IN
does not not drop below 2.0 V.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f. The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground.
g. V
OUT(nom)
is V
OUT
when measured with a 1-V differential to V
IN
.
TIMING WAVEFORMS
FIGURE 1. Timing Diagram for Power-Up
V
SD
0.95 V
NOM
V
OUT
V
NOM
t
ON
0 V
V
IN
t
r
v 1 mS
P1-P3P4-P6P7-P9P10-P10

SI91872DMP-50-E3

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Buy SI91872DMP-50-E3
Manufacturer:
Vishay / Siliconix
Description:
LDO Voltage Regulators 300mA LDO 5.0V w/Error Flag
Lifecycle:
New from this manufacturer.
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