DS1990A-F3+ Datasheet DS1990A-F5+, DS1990A-F3+ | P4-P6

64-Bit Lasered ROM

Each DS1990A contains a unique ROM code that is 64

bits long. The first 8 bits are a 1-Wire family code. The

next 48 bits are a unique serial number. The last 8 bits

are a CRC of the first 56 bits. See Figure 2 for details.

The 1-Wire CRC is generated using a polynomial gen-

erator consisting of a shift register and XOR gates as

shown in Figure 3. The polynomial is X

+ X

+ 1.

Additional information about the 1-Wire Cyclic

Redundancy Check (CRC) is available in Application

Note 27:

Understanding and Using Cyclic Redundancy

Checks with Maxim iButton Products.

The shift register bits are initialized to 0. Then starting

with the least significant bit of the family code, one bit

at a time is shifted in. After the 8th bit of the family code

has been entered, the serial number is entered. After

the 48th bit of the serial number has been entered, the

shift register contains the CRC value. Shifting in the 8

bits of CRC returns the shift register to all 0s.

1-Wire Bus System

The 1-Wire bus is a system that has a single bus master

and one or more slaves. In all instances, the DS1990A

is a slave device. The bus master is typically a micro-

controller or PC. For small configurations, the 1-Wire

communication signals can be generated under soft-

ware control using a single port pin. Alternatively, the

DS2480B 1-Wire line driver chip or serial-port adapters

based on this chip (DS9097U series) can be used. This

simplifies the hardware design and frees the micro-

processor from responding in real time. The discussion

of this bus system is broken down into three topics:

hardware configuration, transaction sequence, and

1-Wire signaling (signal types and timing). The 1-Wire

protocol defines bus transactions in terms of the bus

state during specific time slots that are initiated on the

falling edge of sync pulses from the bus master. For a

more detailed protocol description, refer to Chapter 4 of

the

Book of i

Button Standards

Serial Number i

Button

MSB

8-BIT

CRC CODE

48-BIT SERIAL NUMBER

MSB MSBLSB

LSB

8-BIT FAMILY CODE

(01h)

MSBLSB

Figure 2. 64-Bit Lasered ROM

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

7TH

STAGE

8TH

STAGE

6TH

STAGE

5TH

STAGE

POLYNOMIAL = X

+ X

+ 1

INPUT DATA

Figure 3. 1-Wire CRC Generator

DS1990A

Maxim Integrated

Hardware Configuration

The 1-Wire bus has only a single line by definition; it is

important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device

attached to the 1-Wire bus must have open-drain or

three-state outputs. The 1-Wire port of the DS1990A is

open drain with an internal circuit equivalent to that

shown in Figure 4. A multidrop bus consists of a 1-Wire

bus with multiple slaves attached. At standard speed,

the 1-Wire bus has a maximum data rate of 16.3kbps.

The value of the pullup resistor primarily depends on

the network size and load conditions. For most applica-

tions, the optimal value of the pullup resistor is approxi-

mately 2.2kΩ. The idle state for the 1-Wire bus is high.

If for any reason a transaction needs to be suspended,

the bus must be left in the idle state if the transaction is

to resume. If this does not occur and the bus is left low

for more than 120µs, one or more devices on the bus

may be reset.

Transaction Sequence

The protocol for accessing the DS1990A through the

1-Wire port is as follows:

• Initialization

• ROM Function Command

Initialization

All transactions on the 1-Wire bus begin with an initial-

ization sequence. The initialization sequence consists

of a reset pulse transmitted by the bus master followed

by presence pulse(s) transmitted by the slave(s). The

presence pulse lets the bus master know that the

DS1990A is on the bus and is ready to operate. For

more details, see the

1-Wire Signaling

section.

Serial Number i

Button

PUP

SIMPLE BUS MASTER

DS2480B BUS MASTER

OPEN-DRAIN

PORT PIN

100Ω MOSFET

DATA

DS1990A 1-Wire PORT

Rx = RECEIVE

Tx = TRANSMIT

POL

RXD

SERIAL IN

SERIAL OUT

TXD

GND

N.C.

1-W TO 1-Wire DATA

+5V

HOST CPU

SERIAL

PORT

DS2480B

Figure 4. Hardware Configuration

DS1990A

Maxim Integrated

1-Wire ROM Function Commands

Once the bus master has detected a presence, it can

issue one of the ROM function commands the DS1990A

supports. All ROM function commands are 8 bits long.

A list of these commands follows. (See Figure 5 for a

flowchart.)

Read ROM [33h]

This command allows the bus master to read the

DS1990A’s 8-bit family code, unique 48-bit serial num-

ber, and 8-bit CRC. This command can only be used if

there is a single slave device on the bus. If more than one

slave is present on the bus, a data collision occurs when

all slaves try to transmit at the same time (open drain pro-

duces a wired-AND result). The resultant family code and

48-bit serial number results in a mismatch of the CRC.

Search ROM [F0h]

When a system is initially brought up, the bus master

might not know the number of devices on the 1-Wire

bus or their registration numbers. By taking advantage

of the wired-AND property of the bus, the master can

use a process of elimination to identify the registration

numbers of all slave devices. For each bit of the regis-

tration number, starting with the least significant bit, the

bus master issues a triplet of time slots. On the first slot,

each slave device participating in the search outputs

the true value of its registration number bit. On the sec-

ond slot, each slave device participating in the search

outputs the complemented value of its registration num-

ber bit. On the third slot, the master writes the true

value of the bit to be selected. All slave devices that do

not match the bit written by the master stop participat-

ing in the search. If both of the read bits are zero, the

master knows that slave devices exist with both states

of the bit. By choosing which state to write, the bus

master branches in the ROM code tree. After one com-

plete pass, the bus master knows the registration num-

ber of a single device. Additional passes identify the

registration numbers of the remaining devices. Refer to

Application Note 187:

1-Wire Search Algorithm

for a

detailed discussion, including an example.

Match ROM [55h]/Skip ROM [CCh]

The minimum set of 1-Wire ROM function commands

includes a Match ROM and a Skip ROM command.

Because the DS1990A contains only the 64-bit ROM

without any additional data fields, Match ROM and Skip

ROM are not applicable. The DS1990A remains silent

(inactive) upon receiving a ROM function command

that it does not support. This allows the DS1990A to

coexist on a multidrop bus with other 1-Wire devices

that do respond to Match ROM or Skip ROM.

Serial Number i

Button

DS1990A Tx

PRESENCE PULSE

BUS MASTER Tx

RESET PULSE

BUS MASTER Tx ROM

FUNCTION COMMAND

DS1990A Tx

CRC BYTE

DS1990A Tx

FAMILY CODE

(1 BYTE)

DS1990A Tx

SERIAL NUMBER

(6 BYTES)

33h

READ ROM

COMMAND?

BIT 0 MATCH?

F0h

SEARCH ROM

COMMAND?

DS1990A Tx BIT 0

MASTER Tx BIT 0

BIT 1 MATCH?

BIT 63 MATCH?

DS1990A Tx BIT 1

MASTER Tx BIT 1

DS1990A Tx BIT 63

MASTER Tx BIT 63

Figure 5. ROM Functions Flowchart

DS1990A

Maxim Integrated

P1-P3 P4-P6 P7-P9 P10-P10

DS1990A-F3+

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DS1990A-F3+

DS1990A-F3+

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