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3.3 Device Support Functions
The ATR2732N3 has incorporated some very useful additional functions for handling the device
and optimizing the performance. First of all, a very precise clocking engine is incorporated. To
optimize the performance of this front end, a tuning support for alignment of the filters is featured
by this part too, similar to Atmel’s other radio front ends.
3.4 Tuning Support Functions
The ATR2732N3 includes three operational amplifiers, and three programmable digital-analog
converters (DACs). These outputs are used for automatic filter alignment of the tunable VHF
antenna filter and the preselection filter. DACs are incorporated in the ATR2732N3 for this tun-
ing-support function.
For more details about the usage of the filter-tuning function contact your local Atmel sales office
and ask for the application note covering this feature.
3.5 DAC Usage
There are two DAC modes: pure DAC and Loop/Offset mode. In the pure DAC mode the DAC
sets a definite value. In the Loop/Offset mode the filter tuning voltage is derived from a reference
tank circuit (inductor plus varicap). An offset value can be added to this voltage. This Loop/Off-
set mode is the most useful mode and recommended for most applications. Temperature
compensation is also included in this mode.
3.6 RSSI Measurement
The ATR2732N3 offers the option of getting information about the field strength. This is not an
absolute real-field-strength value, but an indication of in which range the field strength is avail-
able. This information can be obtained from the 8 low bits of the status register.
3.7 Clocking Engine in General
The ATR2732N3 incorporates a convenient and flexible clocking engine. This includes VCOs
and PLLs for both bands, as well as a reference oscillator which can be precisely tuned using
the SPI interface. Together, this results in low external component count, but offers high flexibil-
ity and convenience.
3.8 PLL Part
The two PLL parts, the L-band PLL and the Band III PLL, perform phase lock of the LO signal to
an on-chip crystal reference oscillator. The Band III PLL incorporates a fractional part. This tech-
nique allows operation with an increased bandwidth of the PLL, which results in improved phase
noise.
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3.9 Fast Fractional PLL
The frequency of the VHF VCO is locked to a reference frequency by an on-chip fractional-N
PLL circuit which guarantees superior phase-noise performance. The reference frequencies for
the two PLL blocks are generated by an on-chip oscillator.
The VCOs are fully integrated, which simplifies the design of the device and reduces the bill of
materials of the application.
The LO signal for the first L-band mixer is derived from a PLL-controlled on-chip VCO. The
down-converting to an IF frequency of 38.912 MHz for VHF or converted L-band signal is done
by an additional on-chip VCO using an internal fractional-N PLL.
Due to the digital tuning option of the reference frequency, the ATR2732N3 is able to support the
single reference clock design if the baseband can support such a feature (as the ATR2740
does).
3.10 Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider.
By applying a crystal to the pins XTALA and XTALB, this oscillator generates a highly stable ref-
erence signal.
Furthermore, the frequency of this reference oscillator can be digitally tuned via the SPI bus bits
XOTi (i = 11, ..., 0) with a 12-bit step size.
3.11 Reference Divider
Starting from a minimum value, the scaling factor of the 6-bit reference divider is arbitrarily
programmable by means of the SPI bus bits Ri (i = 5, ..., 0).
The output of this first programmable divider typically provides a 2.048 MHz reference frequency
for the L-band PLL.
A second programmable divider (dividing by 8 to 128) then outputs 64 kHz, which is a useful ref-
erence frequency for the VHF PLL.
Together with the fractional-N PLL, a step size of 16 kHz for the frequency setting of the VHF LO
is ensured.
3.12 Main Divider
The main divider consists of a fully programmable 13-bit divider which defines a division ratio N.
The applied division ratio is either N or N + 1, as specified by a special control unit. On average,
the scaling factors SF = N + k / 4 can be selected where k = 0, 1, 2, or 3.
3.13 Phase Comparator and Charge Pump
The tri-state phase detectors cause the charge pumps to source or sink currents at the output
pins PFDOUTV (for VHF) and PFDOUTL (for L-band) depending on the phase relation of its
input signals, which are provided by the reference and the main dividers, respectively.
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3.14 SPI Bus
The bus interface can be adapted to the signal voltage as a result of the supply voltage of the
external baseband processing unit connected to the bus. This is done with the help of a sensing
pin, VDI, which checks the supply voltage of the processor. The interface adapts itself to any
voltage between 1.65V and 3.5V.
3.14.1 Programming via SPI
Some things need to be taken into account when programming the ATR2732N3 via the SPI
interface: the data packet needs to be properly configured to write into the 14 different registers.
There are 16 registers. Fourteen of them are used to control the ATR2732N3. The two others,
registers 15 and 16, are Test Mode Registers. All these registers need to be reset by writing “0”
to every bit of each register one time, before starting the configuration of the ATR2732N3.
There are 4 address bits (bit 12 is address bit 0; bit 15 is address bit 3) which are used to select
the correct register. These are followed by 12 data bits (LSB is bit 0; MSB is bit 11). There is a
definite transmit order which needs to be considered: the MSB must be transmitted first (bit 15,
address bit 3), and LSB (data bit 0) last.
Unused and test mode register bits may not be documented in the datasheet and have to be set
to “0” in customer applications. Information about the status of the device is available by reading
one word (16 bits) out of the part.
Figure 3-2. Timing Diagram of the SPI Interface (16 Bits per Transfer)
Note: It is absolutely necessary to set the NSS signal back to high after every SPI access.
t
cet
: Clock enable time
t
sud
: Data setup time
t
hda
: Hold time of MOSI
t
per
: Clock period
t
ch
: Clock high time
t
cl
: Clock low time
SCK
t
sud
t
hda
t
per
t
cl
t
ch
t
cet
NSS
MOSI
LSB
MSB *
LSB
MSB
Adress Data
D2D3 D0D1D6D7 D4D5D10D11 D8D9A2A3 A0A1
NSS
SCK
MOSI
MISO

ATR2732N3-PBQW

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
Audio DSPs Integrated DAB One Chip FE, Cons. Vers.
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