EVB-EN5337QI

Enpirion
®
Power Evaluation Board User Guide
EN5337QI
STEP 3: Connect the load to the output connectors VOUT (+) and GND (-), as
indicated in Figure 1.
STEP 4: Select the output voltage setting jumper. You may also set the POK
jumper to include the POK load if POK signal monitoring is intended. The only
time to disable POK is when measuring the absolute Disable current.
Figure 3: Output Voltage selection jumpers
Jumper shown selects 1.2V output
(Jumper positions from left are: 2.5V, 1.55V, 1.0V and 1.2V)
STEP 5: Apply V
IN
to the board and move the ENABLE jumper to the enabled
position. The EN5337QI is now powered up! Various measurements such as
efficiency, line and load regulation, input / output ripple, load transient, drop-out
voltage measurements may be made at this point. The over current trip level,
short circuit protection, under voltage lock out thresholds, temperature coefficient
of the output voltage may also be measured in this configuration.
STEP 5A: Power Up/Down Behavior Remove ENA jumper and connect a
pulse generator (output disabled) signal to the middle pin of ENA and Ground.
Set the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to
10msec. and duty cycle to 50%. Hook up oscilloscope probes to ENA, SS, POK
and VOUT with clean ground returns. Apply power to evaluation board. Enable
pulse generator output. Observe the SS capacitor and VOUT voltage ramps as
ENA goes high and again as ENA goes low. The device when powered down
ramps down the output voltage in a controlled manner before fully shutting down.
The output voltage level when POK is asserted /de-asserted as the device is
powered up / down may be observed as well as the clean output voltage ramp
and POK signals.
Figure 4: Means to Pulse Enable
STEP 6: External Clock Synchronization / Spread Spectrum Modes: In order
to activate this mode, it may be necessary to a solder a SMA connector at J8.
GND
Ext. Enable
4
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Enpirion
®
Power Evaluation Board User Guide
EN5337QI
Alternately the input clock signal leads may be directly soldered to the through
holes of J8 as shown below.
Figure 4: SMA Connector for External Clock Input
Power down the device. Move ENA into disable position. Connect the clock
signal as just indicated. The clock signal should be clean and have a frequency in
the range of 4.5 to 5.5MHz; amplitude 0 to 2.5 volts with a duty cycle between 20
and 80%.
With SYNC signal disabled, power up the device and move ENA jumper to
Enabled position. The device is now powered up and outputting the desired
voltage. The device is switching at its free running frequency. The switching
waveform may be observed between test points SW and GND. Now enabling the
SYNC signal will automatically phase lock the internal switching frequency to the
externally applied frequency as long as the external clock parameters are within
the specified range. To observe phase-lock connect oscilloscope probes to the
input clock as well as to the SW test point. Phase lock range can be determined
by sweeping the external clock frequency up / down until the device just goes out
of lock at the two extremes of its range.
For spread spectrum operation the input clock frequency may be swept between
two frequencies that are within the lock range. The sweep (jitter) repetition rate
should be limited to 10kHz. The radiated EMI spectrum may be now measured in
various states free running, phase locked to a fixed frequency and spread
spectrum.
GND
Ext. Clock
5
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Enpirion
®
Power Evaluation Board User Guide
EN5337QI
Figure 5: EN5337 Evaluation Board Schematic
Output Voltage Select
Programming the Output Voltage.
The EN5337QI output voltage is programmed using a simple resistor divider
network. Figure 6 shows a schematic view of the resistor divider configuration.
The EN5337QI output voltage is determined by the voltage presented at the XFB
pin. The voltage is set by way of a resistor divider between V
OUT
and AGND with
the midpoint going to XFB. A phase lead capacitor is also required across the
upper resistor the one between VOUT and XFB.
R2
C10
TP4
1
C11
J1
1
2
3
J10
1
2
3
R4
TP5
0805
TP3
TP2
J11
1
2
J12
1
2
C9
C12
0402
TP17
TP18
TP17 & TP18 are
used for special
testing. They are
not labeled on PCB.
PVIN
FB1
R3
GND OUT
GND IN
C13
TP12
R6
TP15
J2
1
2
J3
1
2
TP6
TP7
TP13
TP14
J9
1
3
5
2
4
6
87
POK
AVIN
ENA
TP8
TP9
TP10
TP11
TP16
POK
ENA
SS
VOUT
VIN
U2
D1
+
C1
PVIN
VOUT
Add short across R6
when all other
routing is completed
C16
J13
1
2
C17
J14
1
2
R1
R5
R7
J4
C6
C7
XFB
EAOUT
XFB
EAOUT
U1
EN5337Q
NC(SW)
1
NC(SW)
2
NC3
3
NC4
4
VOUT
5
VOUT
6
VOUT
7
VOUT
8
VOUT
9
VOUT
10
VOUT
11
NC(SW)
12
PGND
13
PGND
14
PGND
15
PGND
16
PGND
17
PGND
18
VIN
19
PGND
25
VDDB
24
BTMP
23
PG
22
VIN
21
VIN
20
NC(SW)
38
NC(SW)
37
NC(SW)
36
NC(SW)
35
NC(SW)
34
AVIN
33
AGND
32
XFB
31
SS
30
EAOUT
29
POK
28
ENA
27
SYNC
26
C5
R8
C14
J6
C15
C4
SW
0805
0805
0805
0805
0805
0805
0805
0805
0805
J5
1206/0805
J7
0805
1206/0805
1206
1206
C2
C3
C8
SYNC
1206/0805
1206/0805
1206/0805
TP1
0402
J8
6
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EVB-EN5337QI

Mfr. #:
Manufacturer:
Intel / Altera
Description:
Power Management IC Development Tools Eval Board EN5337QI 3A Sync. Buck Convtr
Lifecycle:
New from this manufacturer.
Delivery:
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