Rev C 2/19/15 10 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
894D115I-01 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50 transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it would be
recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 11 Rev C 2/19/15
894D115I-01 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 894D115I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 894D115I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 80mA = 277.20mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_
MAX
(3.3V, with all outputs switching) = 277mW + 60mW = 337mW
2. Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
Lower temperature refers to ambient temperature, maximum temperature refers to case temperature.
Table 7. Thermal Resistance
JA
for 20 Lead TSSOP, Forced Convection
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.3°C/W 76.9°C/W 74.8°C/W
Rev C 2/19/15 12 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
894D115I-01 DATA SHEET
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω

894D115BGI-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products STM-1/-4 OC-3/-12 CLK/DATA RECOVERY
Lifecycle:
New from this manufacturer.
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