OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 9 Rev C 2/19/15
894D115I-01 DATA SHEET
Parameter Measurement Information, continued
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The 894D115I-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
2 illustrates how a 10 resistor along with a 10F and a 0.01F
bypass capacitor should be connected to each V
CCA
pin.
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
nCLK_OUT,
CLK_OUT,
nDATA_OUT
DATA_OUT
V
CC
V
CCA
3.3V
10µF0.01µF
0.01µF
