ICS87001BGI-01 REVISION A JANUARY 23, 2013 5 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
=V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
IN
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
IN
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 250 MHz
t
PD
Propagation Delay,
Low to High; NOTE 1
N 2 3.6 4.6 5.7 ns
N > 2 4.3 5.5 6.7 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 750 ps
t
R
/t
F
Output Rise/Fall Time 20% to 80% 0.4 0.6 1.0 ns
odc Output Duty Cycle 40 60 %
t
EN
Output Enable Time 10 ns
t
DIS
Output Disable Time 10 ns
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 250 MHz
t
PD
Propagation Delay,
Low to High; NOTE 1
N 2 3.5 4.8 6.2 ns
N > 2 4.5 5.7 6.9 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 590 ps
t
R
/t
F
Output Rise/Fall Time 20% to 80% 0.4 0.7 1.1 ns
odc Output Duty Cycle 40 60 %
t
EN
Output Enable Time 10 ns
t
DIS
Output Disable Time 10 ns
