ICS87001BGI-01 REVISION A JANUARY 23, 2013 7 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
Table 5E. AC Characteristics, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± 0.15V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
IN
250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 250 MHz
t
PD
Propagation Delay,
Low to High; NOTE 1
N 2 3.6 5.2 7.0 ns
N > 2 4.8 6.2 7.7 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 550 ps
t
R
/t
F
Output Rise/Fall Time 20% to 80% 0.5 1.1 2.5 ns
odc Output Duty Cycle 40 60 %
t
EN
Output Enable Time 10 ns
t
DIS
Output Disable Time 10 ns
ICS87001BGI-01 REVISION A JANUARY 23, 2013 8 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
Part-to-Part Skew
SCOPE
Qx
GND
V
DD,
1.65V±5%
-1.65V±5%
V
DDO
SCOPE
Qx
GND
V
DDO
V
DD
0.9V±0.075V
-0.9V±0.075V
2.4V±0.09V
SCOPE
Qx
GND
V
DDO
V
DD
0.9V±0.075V
-0.9V±0.075V
1.6V±0.05V
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
V
DDO
2.05V±5%
SCOPE
Qx
GND
V
DD,
1.25V±5%
-1.25V±5%
V
DDO
Q
Q
tsk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
ICS87001BGI-01 REVISION A JANUARY 23, 2013 9 ©2013 Integrated Device Technology, Inc.
ICS87001I-01 Data Sheet LVCMOS/LVTTL CLOCK DIVIDER
Parameter Measurement Information, continued
Propagation Delay
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Output Enable/Disable Time
Applications Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A1k resistor can be used.
t
PD
V
DD
2
V
DDO
2
Q
CLK0, CLK1
20%
80%
80%
20%
t
R
t
F
Q
Q
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
V
DDO
/2
t
EN
t
DIS
V
DD
/2 V
DD
/2
V
DD
V
OH
0V
V
DDO
/2
Output Q
OE
(High-level
enabling)

87001BGI-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution LVCMOS/LVTTL Clock Divider
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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