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IDT821034DN
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
16
INDUSTRIAL TEMPERATURE RANGE
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Figure 9. Typical Frame Sync Timing (2 MHz Operation)
Serial Control Interface Timing
Parameter
Description
Min
Typ
Max
Units
Test Conditions
t3
1
CS
Hold Time
30
ns
t3
2
CS
Setup Time
30
ns
t3
3
CS
to CO Valid Delay Time
30
ns
t3
4
CO Float Delay Time
10
ns
t3
5
CI Setup Time
30
ns
t3
6
CI Hold Time
30
ns
t37
CS
Idle Tim
e
3
cycles of CCLK
t38
CCLK to CO Valid Delay Time
30
ns
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X0
X1
X2
X3
R0
R1
R2
R3
Time Slot
FS
DX
DR
TSX
Figure 10. SLIC Programming Mode Timing
Note *: CCLK should have one cycle before
CS
goes low, and two cycles after
CS
goes high.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CCLK
CS
CI
CO
t37
Note *
Note *
I/On_0
I/On_1
On_2
On_3
On_4
I/O1_0
I/O2_0
I/O3_0
17
INDUSTRIAL TEMPERATURE RANGE
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CCLK
CS
CI
CO
(High Z)
t37
Figure 11. CODEC Programming Mode Timing
Figure 12. Serial Control Interface Timing
CCLK
CS
CO
CI
t31
t32
t33
t35
t36
t31
t32
t34
t5
t5
t38
18
INDUSTRIAL TEMPERATURE RANGE
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Note *: Whether MSB GA Register is accessed first or LSB GA Register is accessed can be ignored.
Figure 13. Gain Programming Mode Timing
Figure 14. Timing Diagram of the Alternative Method to Read From SLIC Status Register
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
t37
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t37
0
Note *
Note *
CCLK
CS
CI
CO
(High Z)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CCLK
CS
CI
CO
t37
I/On_0
I/On_1
On_2
On_3
On_4
I/O1_0
I/O2_0
I/O3_0
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
IDT821034DN
Mfr. #:
Buy IDT821034DN
Manufacturer:
Description:
IC PCM CODEC QUAD MPI 52QFP
Lifecycle:
New from this manufacturer.
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