7
INDUSTRIAL TEMPERATURE RANGEIDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Table 1. Description of Configuration Register
Table 2. Definition of Time Slot Register
Table 3. Relationship between BCLK Frequency and Time Slot Number
Bit Name Description
7 Register Indicator Always ‘0’
6
5
4
3
2
1
0
Time Slot Bit 6
Time Slot Bit 5
Time Slot Bit 4
Time Slot Bit 3
Time Slot Bit 2
Time Slot Bit 1
Time Slot Bit 0
Bit 6-0 indicate which time slot is selected for the transmit/receive channel. Time
Slot 0 is aligned to FS.
BCLK Frequency 512 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz
Number of Time Slot 8 24 32 64 128
Bit Name Value Description
CR.7 Register Indicator Always ‘1’
CR.6
CR.5
Mode Select 1
Mode Select 0
00
01
10
11
µ
-Law CODEC Mode (This is global setting for all channels.)
A-Law CODEC Mode (This is global setting for all channels.)
SLIC/Gain Mode
Reserved (This mode should not be programmed for normal operation.)
CODEC Mode (CR.6 = ‘0’) Timing Mode Select
0
1
Non-delay Mode (This is global setting for all channels.)
Delay Mode (This is global setting for all channels.)
CR.4
SLIC/Gain Mode (CR.6 = ‘1’) SLIC/Gain Mode Select
0
1
Gain Mode
SLIC Mode
CR.3
CR.2
Channel Address 1
Channel Address 0
00
01
10
11
Select Channel 0 for CODEC or SLIC programming
Select Channel 1 for CODEC or SLIC programming
Select Channel 2 for CODEC or SLIC programming
Select Channel 3 for CODEC or SLIC programming
CODEC Mode (CR.6 = ‘0’)
Transmitter Select
Receiver Select
00
01
10
11
Channel power down
Channel power up with receive time slot assignment
Channel power up with transmit time slot assignment
Channel power up with both receive and transmit time slot assignment
SLIC Mode (CR.6 = ‘1’, CR.4 = ‘1’)
I/O_1 Configuration
I/O_0 Configuration
00
01
10
11
Configure I/O_1 as an output pin and I/O_0 as an output pin
Configure I/O_1 as an output pin and I/O_0 as an input pin
Configure I/O_1 as an input pin and I/O_0 as an output pin
Configure I/O_1 as an input pin and I/O_0 as an input pin
CR.1: Transmit/Receive
Select
0
1
Receive gain will be adjusted
Transmit gain will be adjusted
CR.1
CR.0
Gain Mode (CR.6 = ‘1’, CR.4 = ‘0’)
CR.0: MSB/LSB Select
0
1
Indicates the following 8 bits contain the 7 Least Significant bits of gain
adjustment coefficient
Indicates the following 8 bits contain the 7 Most Significant bits of gain
adjustment coefficient
8
INDUSTRIAL TEMPERATURE RANGEIDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Bit Name Description
7 Register Indicator Always ‘0’
6 -- Reserved, always ‘0’
5 -- Reserved, always ‘0’
4 O_4 Data Output data on O_4 pin of the selected channel
3 O_3 Data Output data on O_3 pin of the selected channel
2 O_2 Data Output data on O_2 pin of the selected channel
1 I/O_1 Data Output data on I/O_1 pin (if defined as an output) of the selected channel
0 I/O _0 Data Output data on I/O_0 pin (if defined as an output) of the selected channel
Table 4. Definition of SLIC Control Register
Bit Name Description
7 I/On_0 Image Mapped to I/On_0 pin of the selected channel n
6 I/On_1 Image Mapped to I/On_1 pin of the selected channel n
5 On_2 Image Mapped to On_2 pin of the selected channel n
4 On_3 Image Mapped to On_3 pin of the selected channel n
3 On_4 Image Mapped to On_4 pin of the selected channel n
2 I/O1_0 Image Always mapped to the I/O1_0 pin
1 I/O2_0 Image Always mapped to the I/O2_0 pin
0 I/O3_0 Image Always mapped to the I/O3_0 pin
Table 5. Definition of SLIC Status Register
APPLICATION NOTE
The IDT821034 is mainly used in line card application. Figure 5 shows
a typical system with telephony line interface.
The IDT821034 offers not only encoding/decoding function, but also a
signaling channel, which can simplify the circuit design of the control
interface. In addition, the dynamic time slot assignment of IDT821034
reduces the hardware requirement for PCM interface. The device also
supports 8.192 Mbps PCM data rate, which can increase the time slot
density up to 128.
Signal to total distortion ratio (both STD
X
and STD
R
) are guaranteed
over -55 dBm0 to +3 dBm0 range with a specific gain setting (0 dB for both
transmit path and receive path). Since there is a finite noise floor associated
with the quantization effect of both data converters and digital filter
coefficients, the overall signal to total distortion ratio of each path is a function
of the gain setting. In system design, attention should be paid to the gain
setting for the best signal to total distortion performance.
Generally, a channel gain of a line-card system is contributed
by both SLIC and CODEC. In a system design using IDT821034, the
SLIC gain should be taken into account to optimize the SNR. In the transmit
path of IDT821034, there are two resistors (R1 and R3 in Figure 5)
which enable the analog gain to be adjusted around 0 dB. Further gain
adjustment can be obtained by programming the DSP filters. Since this
adjustment is close to 0 dB, the SNR remains at the optimum value. In
the receive path of IDT821034, analog gain adjustment is not available.
Thus, the adjustment of CODEC gain will be performed only by
programming the DSP filters. In this way, the SLIC gain should be such
that the DSP gain is closest to 0 dB. This will maximize the achievable
SNR in the overall system. For example, if the design target for receive
path gain is -3.5 dB and -7 dB for local and long distance calls
respectively, the recommended solution is to set SLIC gain at -3.5 dB.
As a result, the gain of CODEC, which is adjusted by programming DSP
coefficients, will be 0 dB and -3.5 dB.
9
INDUSTRIAL TEMPERATURE RANGEIDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Figure 5. Typical Application Circuit
Note:
1. Recommended value for R1 is between 40 k and 100 k.
2. The value of R3 is chosen to implement the desired transmit gain.
The CODEC Transmit Gain = R1/R3.
3. The value of R2 is chosen to cancel the echo due to hybrid and
impedance mismatch. Assume the receive level is VFRO(t) and the 4-line
output with SLIC input properly terminated is V4out(t), the value of R2
should be chosen as follows:
VFRO(t)/R2 = V4out(t)/R3
VDD
CNF
DX
DR
TSX
FS
MCLK
BCLK
CO
CI
CS
CCLK
I
D
T
8
2
1
0
3
4
+5V SUPPLY
VFRO
VDDA
GNDA
GND
I/O0_1
I/O0_0
VFXI
O0_2
O0_3
O0_4
CH0 SLIC
GSX0
K1 K2 K3K3
2k
2k
2k
VCC
0.1µF
0.1µF
68K R1
R2
R3
off / on hook
line reverse
Ring
Tip
Test BUS
Ring BUS
protector
K1
K2K3
V4out
V4in
Control Bus
PCM Bus
4
6
5
5
100
100
100 100

IDT821034DN

Mfr. #:
Manufacturer:
Description:
IC PCM CODEC QUAD MPI 52QFP
Lifecycle:
New from this manufacturer.
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