© 2006 Microchip Technology Inc. DS21394C-page 5
TC14433/A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin No.
(24-Pin PDIP)
(24-Pin CERDIP)
(24-Pin SOIC)
Pin No.
(28-Pin
PLCC)
Symbol Description
12V
AG
This is the analog ground. It has a high input impedance. The pin determines
the reference level for the unknown input voltage (V
X
) and the reference
voltage (V
REF
).
23V
REF
Reference voltage – Full scale output is equal to the voltage applied to V
REF
.
Therefore, full scale voltage of 1.999V requires 2V reference and 199.9 mV
full scale requires a 200 mV reference. V
REF
functions as system reset also.
When switched to V
EE
, the system is reset to the beginning of the
conversion cycle.
34V
X
The unknown input voltage (V
X
) is measured as a ratio of the reference
voltage (V
REF
) in a ratiometric A/D conversion.
45R
1
This pin is for external components used for the integration function in the
dual slope conversion. Typical values are 0.1 μF (Mylar) capacitor for C
1
.
56R
1
/C
1
R
1
= 470 kΩ (resistor) for 2V full scale.
67C
1
R
1
= 27 kΩ (resistor) for 200 mV full scale. Clock frequency of 66 kHz gives
250 msec conversion time.
79CO
1
These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1 μF.
810CO
2
These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1 μF.
9 11 DU Display update input pin. When DU is connected to the EOC output, every
conversion is displayed. New data will be strobed into the output latches
during the conversion cycle if a positive edge is received on DU, prior to the
ramp down cycle. When this pin is driven from an external source, the
voltage should be referenced
to V
SS
.
10 12 CLK
1
Clock input pins. The TC14433 has its own oscillator system clock.
Connecting a single resistor between CLK
1
and CLK
0
sets the clock
frequency.
11 13 CLK
0
A crystal or OC circuit may be inserted in lieu of a resistor for improved
CLK
1
, the clock input, can be driven from an external clock source, which
need only have standard CMOS output drive. This pin is referenced to V
EE
for external clock inputs. A 300 kΩ resistor yields a clock frequency of about
66 kHz. See Section 3.0 “Typical Characteristics”. (Also see Figure for
alternate circuits.)
12 14 V
EE
Negative power current. Connection pin for the most negative supply. Please
note the current for the output drive circuit is returned through V
SS
. Typical
supply current is 0.8 mA.
13 16 V
SS
Negative power supply for output circuitry. This pin sets the low voltage level
for the output pins (BCD, Digit Selects, EOC, OR). When connected to
analog ground, the output voltage is from analog ground to V
DD
. If
connected to V
EE
, the output swing is from V
EE
to V
DD
. The recommended
operating range for V
SS
is between the V
DD
-3 volts and V
EE
.
14 17 EOC End of conversion output generates a pulse at the end of each conversion
cycle. This generated pulse width is equal to one half the period of the
system clock.
