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CY2310ANZPVXC-1T

P1-P3P4-P6P7-P8
3.3V SDRAM Buffer for Mobile PCs
with 4 SO-DIMMs
CY2310ANZ
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07142 Rev. *B Revised January 19, 2005
1CY2310NZCY2310
NZCY2310ANZ
Features
• One input to 10 output buffer/driver
• Supports up to four SDRAM SO-DIMMs
• Two additional outputs for feedback
• Serial interface for output control
• Low skew outputs
• Up to 100-MHz operation
•Multiple V
DD
and V
SS
pins for noise reduction
• Dedicated OE pin for testing
• Space-saving 28-pin SSOP package
• 3.3V operation
Functional Description
The CY2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has 10
outputs, 8 of which can be used to drive up to four SDRAM
SO-DIMMs, and the remaining can be used for external
feedback to a PLL. The device operates at 3.3V and outputs
can run up to 100 MHz, thus making it compatible with
Pentium II
®
processors. The CY2310ANZ can be used in
conjunction with the CY2281 or similar clock synthesizer for a
full Pentium II motherboard solution.
The CY2310ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled. A separate Output Enable pin facilitates
testing on ATE.
Block Diagram
Serial Interface
BUF_IN
SDATA
SCLOCK
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
1
2
3
4
V
DD
SDRAM7
SDRAM6
V
SS
V
DD
SDRAM5
28-pin SSOP
Top View
Pin Configuration
Decoding
8
5
6
7
12
9
10
11
13
14
28
27
26
25
21
24
23
22
17
20
19
18
16
15
SDRAM4
V
SS
OE
V
DD
SDRAM9
V
SS
V
SSIIC
SCLOCK
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
V
SS
BUF_IN
V
DD
SDRAM8
V
SS
V
DDIIC
SDATA
SDRAM3
SDRAM8
SDRAM9
OE
[+] Feedback
CY2310ANZ
Document #: 38-07142 Rev. *B Page 2 of 8
Device Functionality
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• Serial interface address for the CY2310ANZ is:
Pin Summary
Name Pins Description
V
DD
1, 5, 10, 19, 24, 28 3.3V Digital voltage supply
V
SS
4, 8, 12, 17, 21, 25 Ground
V
DDIIC
13 Serial interface voltage supply
V
SSIIC
16 Ground for serial interface
BUF_IN 9 Input clock
OE 20 Output Enable, three-states outputs when LOW. Internal pull-up to V
DD
SDATA 14 Serial data input, internal pull-up to V
DD
SCLK 15 Serial clock input, internal pull-up to V
DD
SDRAM [0–3] 2, 3, 6, 7 SDRAM byte 0 clock outputs
SDRAM [4–7] 22, 23, 26, 27 SDRAM byte 1 clock outputs
SDRAM [8–9] 11, 18 SDRAM byte 2 clock outputs
OE SDRAM [0–17]
0 High-Z
1 1 x BUF_IN
A6 A5 A4 A3 A2 A1 A0 R/W
1101001----
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enabled
Bit Pin # Description
Bit 7 -- Initialize to 0
Bit 6 -- Initialize to 0
Bit 5 -- Initialize to 0
Bit 4 -- Initialize to 0
Bit 3 7 SDRAM3 (Active/Inactive)
Bit 2 6 SDRAM2 (Active/Inactive)
Bit 1 3 SDRAM1 (Active/Inactive)
Bit 0 2 SDRAM0 (Active/Inactive)
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description
Bit 7 27 SDRAM7 (Active/Inactive)
Bit 6 26 SDRAM6 (Active/Inactive)
Bit 5 23 SDRAM5 (Active/Inactive)
Bit 4 22 SDRAM4 (Active/Inactive)
Bit 3 -- Initialize to 0
Bit 2 -- Initialize to 0
Bit 1 -- Initialize to 0
Bit 0 -- Initialize to 0
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description
Bit 7 18 SDRAM9 (Active/Inactive)
Bit 6 11 SDRAM8 (Active/Inactive)
Bit 5 -- Reserved, drive to 0
Bit 4 -- Reserved, drive to 0
Bit 3 -- Reserved, drive to 0
Bit 2 -- Reserved, drive to 0
Bit 1 -- Reserved, drive to 0
Bit 0 -- Reserved, drive to 0
[+] Feedback
CY2310ANZ
Document #: 38-07142 Rev. *B Page 3 of 8
Maximum Ratings
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except BUF_IN)........–0.5V to V
DD
+ 0.5V
DC Input Voltage (BUF_IN)............................ –0.5V to +7.0V
Storage Temperature ................................. –65
°C to +150°C
Junction Temperature................................................. 150
°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions
Parameter Description Min. Max. Unit
V
DD
Supply Voltage 3.135 3.465 V
T
A
Operating Temperature (Ambient Temperature) 0 70 °C
C
L
Load Capacitance 20 30 pF
C
IN
Input Capacitance 7 pF
t
PU
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
0.05 50 ms
Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
V
IL
Input LOW Voltage
[1]
Except serial interface pins 0.8 V
V
ILiic
Input LOW Voltage For serial interface pins only 0.7 V
V
IH
Input HIGH Voltage
[1]
2.0 V
I
IL
Input LOW Current
(BUF_IN input)
V
IN
= 0V –10 10 µA
I
IL
Input LOW Current
(Except BUF_IN Pin)
V
IN
= 0V 100 µA
I
IH
Input HIGH Current V
IN
= V
DD
–10 10 µA
V
OL
Output LOW Voltage
[2]
I
OL
= 25 mA 0.4 V
V
OH
Output HIGH Voltage
[2]
I
OH
= –36 mA 2.4 V
I
DD
Supply Current
[2]
Unloaded outputs, 100-MHz 200 mA
I
DD
Supply Current Loaded outputs, 100-MHz 360 mA
I
DD
Supply Current
[2]
Unloaded outputs, 66.67-MHz 150 mA
I
DD
Supply Current Loaded outputs, 66.67-MHz 230 mA
I
DDS
Supply Current BUF_IN=V
DD
or V
SS
All other inputs at V
DD
500 µA
Notes:
1. BUF_IN input has a threshold voltage of V
DD
/2.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
[+] Feedback
P1-P3P4-P6P7-P8

CY2310ANZPVXC-1T

Mfr. #:
Buy CY2310ANZPVXC-1T
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3V Non Zero Delay SDRAM Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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