CY2310ANZ
Document #: 38-07142 Rev. *B Page 6 of 8
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Summary
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance
of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board V
DD
from the clock generator V
DD
island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
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