IDT
®
Frequency Timing Generator for Peripherals 1604C—04/23/15
9FGP204
Frequency Timing Generator for Peripherals
2
Pin Description
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1 GND PWR Ground pin.
2 VDD96 PWR Power pin for the DOT96 clocks, nominal 3.3V
3DOT96SST OUT
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are
current mode outputs. External resistors are required for voltage bias.
4DOT96SSC OUT
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
These are current mode outputs. External resistors are required for voltage bias.
5OE_96 IN
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 =disable output(s)
6OE_CPU IN
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 =disable output(s)
7 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
8 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
9 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
10 GNDCPU PWR Ground pin for the CPU outputs
11 IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It requires a
fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential
impedance. Other impedances require different values. See data sheet.
12 VDD32K PWR Power pin for the 32.768KHz outputs, nominal 3.3V
13 32.768KHz OUT 32.768KHz clock output
14 GND32K PWR Ground pin for the 32.768KHz outputs
15 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
16 25MHz_0 OUT 25MHz clock output, 3.3V
17 25MHZ_1 OUT 25MHz clock output, 3.3V
18 GNDREF PWR Ground pin for the REF outputs.
19 X1_25 IN Crystal input, Nominally 25.00MHz.
20 X2_25 OUT Crystal output.
21 GND33 PWR Ground pin for the 33.33MHz outputs
22 33.33MHZ/**SMBADR I/O 33.33MHz clock output / SMBus address select bit.
23 VDD33 PWR Power pin for the 33.33MHz outputs, nominal 3.3V
24 RMII5 OUT 3.3V 50MHz RMII clock output
25 RMII4 OUT 3.3V 50MHz RMII clock output
26 VDDRMII PWR 3.3V power pin for the RMII clocks.
27 GNDRMII PWR Ground pin for the RMII outputs
28 RMII3 OUT 3.3V 50MHz RMII clock output
29 RMII2 OUT 3.3V 50MHz RMII clock output
30 GNDRMII PWR Ground pin for the RMII outputs
31 VDDRMII PWR 3.3V power pin for the RMII clocks.
32 RMII1 OUT 3.3V 50MHz RMII clock output
33 RMII0 OUT 3.3V 50MHz RMII clock output
34 VDDRGMII PWR 3.3V power pin for the RGMII clocks and PLL
35 GNDRGMII PWR Ground pin for the RGMII outputs
36 RGMII1 OUT 3.3V 125MHz RGMII clock output
37 RGMII0 OUT 3.3V 125MHz RGMII clock output
38 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
39 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
40 VttPwr_GD/PD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
