9FGP204BKLFT Datasheet 9FGP204BKLFT, 9FGP204BKLF | P13-P15

IDT

Frequency Timing Generator for Peripherals 1604C—04/23/15

9FGP204

Frequency Timing Generator for Peripherals

SMBus Table: CPU Frequency Select and Spread Spectrum Control Register

te 0 Name Control Function T

e0 1 PWD

Bit 7

Reserved Reserved RW 0

Bit 6

Reserved Reserved Rev 0.20 0

Bit 5

Reserved Reserved RW 0

Bit 4

DOT96 SS_EN DOT96 Spread Spectrum Enable RW Disable Enable 0

Bit 3

CPU SS_EN CPU Spread Spectrum Enable RW 0

Bit 2

CPU FS2 CPU Freq Select Bit 2 RW 1

Bit 1

CPU FS1 CPU Freq Select Bit 1 RW 0

Bit 0

CPU FS0 CPU Freq Select Bit 0 RW 1

SMBus Table: RMII Output Control Register

te 1 Name Control Function T

e0 1 PWD

Bit 7

RMII_5 Enable RMII_7 Output Control RW Disable Enable 1

Bit 6

RMII_4 Enable RMII_6 Output Control RW Disable Enable 1

Bit 5

RMII_3 Enable RMII_5 Output Control RW Disable Enable 1

Bit 4

RMII_2 Enable RMII_4 Output Control RW Disable Enable 1

Bit 3

RMII_1 Enable RMII_3 Output Control RW Disable Enable 1

Bit 2

RMII_0 Enable RMII_2 Output Control RW Disable Enable 1

Bit 1

RGMII_1 Enable RGMII_1 Output Control RW Disable Enable 1

Bit 0

RGMII_0 Enable RGMII_0 Output Control RW Disable Enable 1

SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register

te 2 Name Control Function T

e0 1 PWD

Bit 7

CPUCLK PD Drive Mode Driven in PD RW Driven Hi-Z 0

Bit 6

DOT96SS PD Drive

Mode

Driven in PD RW Driven Hi-Z 0

Bit 5

33.33MHz Enable 33.33MHz Output Control RW Disable Enable 1

Bit 4

25MHz_1 Enable 25MHz_1 Output Control RW Disable Enable 1

Bit 3

25MHz_0 Enable 25MHz_0 Output Control RW Disable Enable 1

Bit 2

32.768kHz Enable 32.768KHz Output Control RW Disable Enable 1

Bit 1

CPUCLK Enable CPUCLK Output Control RW Disable Enable 1

Bit 0

DOT96SS Enable DOT96SS Output Control RW Disable Enable 1

SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register

te 3 Name Control Function T

e0 1 PWD

Bit 7

Reserved Reserved RW 0

Bit 6

Reserved Reserved RW 0

Bit 5

Reserved Reserved RW 0

Bit 4

Reserved Reserved RW 0

Bit 3

DOT96SS FS3 DOT96 Freq Select Bit 3 RW 0

Bit 2

DOT96SS FS2 DOT96 Freq Select Bit 2 RW 0

Bit 1

DOT96SS FS1 DOT96 Freq Select Bit 1 RW 0

Bit 0

DOT96SS FS0 DOT96 Freq Select Bit 0 RW 0

SMBus Table: RMII Strength Control Register

te 4 Name Control Function T

e0 1 PWD

Bit 7

RMII_5 Str RMII_7 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 6

RMII_4 Str RMII_6 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 5

RMII_3 Str RMII_5 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 4

RMII_2 Str RMII_4 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 3

RMII_1 Str RMII_3 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 2

RMII_0 Str RMII_2 Strength Control RW 1-Load (1X) 2-Loads (2X) 0

Bit 1

Reserved Reserved RW 0

Bit 0

Reserved Reserved RW 0

Reserved

7,8

3,4

Pin #

- Reserved

Reserved

Pin #

Reserved

See Table 1:

CPU Frequency Selection

Table

Reserved

Pin #

See Table 2:

DOT Frequency Selection

Table

IDT

Frequency Timing Generator for Peripherals 1604C—04/23/15

9FGP204

Frequency Timing Generator for Peripherals

SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register

te 5 Name Control Function T

e0 1 PW

Bit 7

Reserved Reserved RW Reserved 0

Bit 6

Reserved Reserved RW Reserved 0

Bit 5

33.33MHz Str 33.33MHz Strength Control RW 1-Load (1X) 2-Loads (2X) 1

Bit 4

25MHz_1 Str 25MHz_1 Strength Control RW 1-Load (1X) 2-Loads (2X) 1

Bit 3

25MHz_0 Str 25MHz_1 Strength Control RW 1-Load (1X) 2-Loads (2X) 1

Bit 2

32.768kHz Str 32.768kHz Strength Control RW 1-Load (1X) 2-Loads (2X) 1

Bit 1

Reserved Reserved RW Reserved 0

Bit 0

Reserved Reserved RW Reserved 0

SMBus Table: Vendor & Revision ID Register

te 6 Name Control Function T

e0 1 PW

Bit 7

RID3 R X

Bit 6

RID2 R X

Bit 5

RID1 R X

Bit 4

RID0 R X

Bit 3

VID3 R 0

Bit 2

VID2 R 0

Bit 1

VID1 R 0

Bit 0

VID0 R 1

SMBus Table: Device ID

te 7 Name Control Function T

e0 1 PW

Bit 7

Device ID 7 (MSB) RW 0

Bit 6

Device ID 6 RW 0

Bit 5

Device ID 5 RW 1

Bit 4

Device ID 4 RW 0

Bit 3

Device ID 3 RW 0

Bit 2

Device ID 2 RW 1

Bit 1

Device ID 1 RW 0

Bit 0

Device ID 0 (LSB) RW 0

SMBus Table: Byte Count Register

te 8 Name Control Function T

e0 1 PW

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 1

Bit 2

BC2 RW - - 0

Bit 1

BC1 RW - - 0

Bit 0

BC0 RW - - 1

SMBus Table: Reserved

te 9 Name Control Function T

e0 1 PW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ICS/IDT = 0001

A rev = 0000

B rev = 0001

Reserved

Pin #

Reserved

REVISION ID

VENDOR ID

Pin #

Reserved

Writing to this register configures

how many bytes will be read back.

Pin #

Device ID

Reserved

Pin #

Reserved

IDT

Frequency Timing Generator for Peripherals 1604C—04/23/15

9FGP204

Frequency Timing Generator for Peripherals

SMBus Table: PLLs M/N Programming Enable Register

te 10 Name Control Function T

e0 1 PW

Bit 7

M/N_EN PLLs M/N Programming Enable RW Disable Enable 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: CPU PLL VCO Frequency Control Register

te 11 Name Control Function T

e0 1 PW

Bit 7

N Div8 N Divider Prog bit 8 RW X

Bit 6

N Div 9 N Divider Prog bit 9 RW X

Bit 5

M Div5 RW X

Bit 4

M Div4 RW X

Bit 3

M Div3 RW X

Bit 2

M Div2 RW X

Bit 1

M Div1 RW X

Bit 0

M Div0 RW X

SMBus Table: CPU PLL VCO Frequency Control Register

te 12 Name Control Function T

e0 1 PW

Bit 7

N Div7 RW X

Bit 6

N Div6 RW X

Bit 5

N Div5 RW X

Bit 4

N Div4 RW X

Bit 3

N Div3 RW X

Bit 2

N Div2 RW X

Bit 1

N Div1 RW X

Bit 0

N Div0 RW X

SMBus Table: CPU PLL Spread Spectrum Control Register

te 13 Name Control Function T

e0 1 PW

Bit 7

SSP7 RW X

Bit 6

SSP6 RW X

Bit 5

SSP5 RW X

Bit 4

SSP4 RW X

Bit 3

SSP3 RW X

Bit 2

SSP2 RW X

Bit 1

SSP1 RW X

Bit 0

SSP0 RW X

SMBus Table: CPU PLL Spread Spectrum Control Register

te 14 Name Control Function T

e0 1 PW

Bit 7

Bit 6

SSP14 RW X

Bit 5

SSP13 RW X

Bit 4

SSP12 RW X

Bit 3

SSP11 RW X

Bit 2

SSP10 RW X

Bit 1

SSP9 RW X

Bit 0

SSP8 RW X-

Pin #

These Spread Spectrum bits

in Byte 13 and 14 will

program the spread

pecentage. It is

recommended to use ICS

Spread % table for spread

programming.

Reserved

Spread Spectrum Programming

b(7:0)

M Divider Programming bits

Pin #

Spread Spectrum Programming

b(14:8)

Pin #

Reserved

These Spread Spectrum bits

in Byte 13 and 14 will

program the spread

pecentage. It is

recommended to use ICS

Spread % table for spread

programming.

Reserved

The decimal representation

of M and N Divier in Byte 11

and 12 will configure the

VCO frequency. Default at

power up = latch-in or Byte 0

Rom table. VCO Frequency

= 25 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

N Divider Programming b(7:0)

The decimal representation

of M and N Divier in Byte 11

and 12 will configure the

VCO frequency. Default at

power up = latch-in or Byte 0

Rom table. VCO Frequency

= 25 x [NDiv(9:0)+8] /

[MDiv(5:0)+2]

Reserved

Pin #

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9FGP204BKLFT

Mfr. #:

Buy 9FGP204BKLFT

Manufacturer:

IDT

Description:

Clock Generators & Support Products CK-MNG SERVER PERIPH ERAL CLOCK

Lifecycle:

New from this manufacturer.

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9FGP204BKLFT

9FGP204BKLFT

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