LTC2486
25
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For more information www.linear.com/LTC2486
APPLICATIONS INFORMATION
Figure 11. Internal Serial Clock, Continuous Operation
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris
-
ing edge of SCK (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is floating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2486’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal
SCK timing mode.
EOC
CS
SCK
(INTERNAL)
SDI
SDO
2486 F11
CONVERSION
DATA INPUT/OUTPUT
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
BIT 10 BIT 9 BIT 0
2 31 4 5 6 7 8 9 10 11 12 13 14 15 16 24
DON'T CAREDON'T CARE
MSBSIG“0”
V
CC
f
O
SCK
SDI
SDO
CS
GND
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2486
3-WIRE
SPI INTERFACE
OPTIONAL
10k
V
CC
REF
+
REF
CH0
CH1
CH2
CH3
COM
12 1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1µF
10µF
CONVERSION
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver
-
sion status. If the device is in the sleep state (EOC = 0),
SCK
will go LOW. If CS goes HIGH before the time t
EOCtest
,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2486 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
LTC2486
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For more information www.linear.com/LTC2486
Digital Signal Levels
The LTC2486’s digital interface is easy to use. Its digital
inputs SDI, f
O
, CS, and SCK (in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as 100µs.
The digital input signal range is 0.5V to V
CC
– 0.5V. During
transitions, the CMOS input circuits draw dynamic cur-
rent. For
optimal
performance, application of signals to
the serial data interface should be reserved for the sleep
and data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital
interface and the external oscillator pin (f
O
) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difficult when shared control lines
are used and
multiple
reflections occur.
APPLICATIONS INFORMATION
Parallel termination near the input pin of the LTC2486 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depend
-
ing on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, f
O
) remain static during the conversion cycle and no
degradation occurs. On the other hand, if an external
oscillator is used (f
O
driven externally) it is active during
the conversion cycle. Moreover, the digital filter rejection
is minimal at the clock rate applied to f
O
. Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
Driving the Input and Reference
The input and reference pins of the LTC2486 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge
is transferred. A simplified equivalent circuit is
shown in Figure 12.
Figure 12. LTC2486 Equivalent Analog Input Circuit
IN
+
IN
10k
INTERNAL
SWITCH
NETWORK
10k
C
EQ
12pF
10k
I
IN
REF
+
I
REF
+
I
IN
+
I
REF
2486 F12
SWITCHING FREQUENCY
f
SW
= 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 • f
EOSC
EXTERNAL OSCILLATOR
REF
10k
100Ω
INPUT
MULTIPLEXER
100Ω
I IN
+
( )
AVG
= I IN
( )
AVG
=
V
IN(CM)
V
REF(CM)
0.5R
EQ
I REF
+
( )
AVG
1.5V
REF
+ V
REF(CM)
V
IN(CM)
( )
0.5R
EQ
V
IN
2
V
REF
R
EQ
where:
V
REF
=REF
+
REF
V
REF(CM)
=
REF
+
REF
2
V
IN
=IN
+
IN
,WHERE IN
+
ANDIN
ARE THE SELECTEDINPUT CHANNELS
V
IN(CM)
=
IN
+
IN
2
R
EQ
= 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
R
EQ
= 2.98MΩINTERNAL OSCILLATOR 50Hz/60Hz MODE
R
EQ
= 0.83310
12
( )
/f
EOSC
EXTERNAL OSCILLATOR
LTC2486
27
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For more information www.linear.com/LTC2486
APPLICATIONS INFORMATION
When using the LTC2486’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
than 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low imped
-
ance source. In this case, complete settling occurs even
with
large external bypass capacitors. The inputs (CH0 to
CH3, COM), on the other hand, are typically driven from
larger source resistances. Source resistances up to 10k
may interface directly to the LTC2486 and settle completely;
however, the addition of external capacitors at the input
terminals in order to filter unwanted noise (anti-aliasing)
results in incomplete settling.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than
the 580ns required
for
1ppm accuracy. For example, a 10bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2486 uses a proprietary switching algorithm that
forces the average differential input current to zero indepen
-
dent of external settling errors. This allows direct digitization
of high impedance sensors without the need of buffers.
The switching algorithm forces the average input current
on the positive input (I
IN
+
) to be equal to the average input
current on the negative input (I
IN
). Over the complete
conversion cycle, the average differential input current
(I
IN
+
I
IN
) is zero. While the differential input current is
zero, the common mode input current (I
IN
+
+ I
IN
)/2 is
proportional to the difference between the common mode
input voltage (V
IN(CM)
) and the common mode reference
voltage (V
REF(CM)
).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com
-
mon mode input currents are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode
voltage is
constant
but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
IN(CM)
and V
REF(CM)
. For a reference
common mode voltage of 2.5V and an input common
mode of 1.5V, the common mode input current is ap
-
proximately 0.74µA. This common mode input current
does not degrade the accuracy if the source impedances
tied to IN
+
and IN
are matched. Mismatches in source
impedance lead to a fixed offset error but do not effect
the linearity or full scale reading. A 1% mismatch in a 1k
source resistance leads to a 74µV shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single ended
type sensors), the common mode input current varies pro
-
portionally with input
voltage. For the case of balanced input
impedances, the common mode input current effects are
rejected by the large CMRR of the LTC2486, leading to little
degradation in accuracy. Mismatches in source impedances
lead to gain errors proportional to the difference between
the common mode input and common mode reference. 1%
mismatches
in 1k source resistances lead to gain errors on
the order of 15ppm. Based on the stability of the internal
sampling capacitors and the accuracy of the internal oscil
-
lator, a one-time calibration will remove this error.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA Max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Reference Current
Similar to the analog inputs, the LTC2486 samples the
differential reference pins (REF
+
and REF
) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete set
-
tling occurs (as a function the reference source resistance

LTC2486CDE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit, 4-ch Delta Sigma ADC w/ Temp Sensor PGA
Lifecycle:
New from this manufacturer.
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