EL5625ILZ-T13 Datasheet EL5625ILZ-T13, EL5625ILZ | P10-P12

FN7488.1

February 20, 2008

CHANNEL OUTPUTS

Each of the channel outputs has a rail-to-rail buffer. This

enables all channels to have the capability to drive to within

50mV of the power rails, (see Electrical Characteristics for

details).

When driving large capacitive loads, a series resistor should

be placed in series with the output (Usually between 5 and

50).

Each of the channels is updated on a continuous cycle, the

time for the new data to appear at a specific output will

depend on the exact timing relationship of the incoming data

to this cycle.

The best-case scenario is when the data has just been

captured and then passed on to the output stage

immediately; this can be as short as 48µs. In the worst-case

scenario, this will be 860µs for EL5625, when the data has

just missed the cycle at f_OSC = 21kHz.

When a large change in output voltage is required, the

change will occur in 2V steps, thus the requisite number of

timing cycles will be added to the overall update time. This

means that a large change of 16V can take between 6.8ms

and 7.2ms depending on the absolute timing relative to the

update cycle.

Output Stage and the Use of External

Oscillator

Simplified output sample and hold amp stage for one

channel.

The output voltage is generated from the DAC, which is V

in the above circuit. The refreshed switches are controlled by

the internal or external oscillator signal. When the OSC clock

signal is low, switches S

and S

are closed. The output

OUT

= V

and at the same time the sample and hold cap

CH is being charged. When the OSC clock signal is high, the

refreshed switches S

and S

are opened and the output

voltage is maintained by CH. This refreshed process will

repeat every 18 clock cycles for each channel. The time

takes to update the output depends on the timing at the V

and the state of the switches. It can take 1 to 19 clock cycles

to update each output.

For the sample and hold capacitor CH to maintain the

correct output voltage, the driving load shouldn’t be changed

at the rising edge of the OSC signal. Since at the rising edge

of the OSC clock, the refreshed switches are being opened,

if the load changes at that time, it will generate an error

output voltage. For a fixed load condition, the internal

oscillator can be used.

For the transient load condition, the external OSC mode

should be used to avoid the conflict between the rising edge

of the OSC signal and the changing load. So a timing delay

circuit will be needed to delay the OSC signal and avoid the

rising edge of the OSC signal and changing the load at the

same time.

TRANSIENT LOAD RESPONSE

Channel 3 --- sinking and sourcing 5mA current

Channel 2 --- EXT_OSC signal

Channel 1 --- V

OUT

Here, the OSC signal is synchronized to the load signal. The

rising edge of the OSC signal is then delayed by some

amount of time and gives enough time for CH to be charged

to a new voltage before the switches are opened.

CHANNEL TO CHANNEL REFRESH

Ch1 --- Output1

Ch3 --- Output2

Ch2 --- EXT_OSC

OUT

1.3V

FIGURE 8.

OSC

1.3V

FIGURE 9.

FIGURE 10.

EL5625

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FN7488.1

February 20, 2008

At the falling edge of the OSC, output 1 is being refreshed

and one clock cycle later, output 2 is being refreshed. The

spike you see here is the response of the output amplifier

when the refreshed switches are closed. When driving a big

capacitor load, there will be ringing at the spikes because

the phase margin of the amplifier is decreased.

The speed of the external OSC signal shouldn’t be greater

than 70kHz because for the worst condition, it will take at

least 4µs to charge the sample and hold capacitor CH. The

pulse width has to be at least 4µs long. From our lab test, the

duty cycle of the OSC signal must be greater than 30%.

POWER DISSIPATION

With the 100mA maximum continues output drive capability

for V

COM

channel, it is possible to exceed the 125°C

absolute maximum junction temperature. Therefore, it is

important to calculate the maximum junction temperature for

the application to determine if load conditions need to be

modified for the part to remain in the safe operation.

The maximum power dissipation allowed in a package is

determined according to:

where:

•T

JMAX

= Maximum junction temperature

•T

AMAX

= Maximum ambient temperature

• 

= Thermal resistance of the package

•P

DMAX

= Maximum power dissipation in the package

The maximum power dissipation actually produced by the IC

is the total quiescent supply current times the total power

supply voltage and plus the power in the IC due to the loads.

when sourcing, and:

when sinking.

Where:

• i = 18

•V

= Supply voltage

•I

= Quiescent current

•V

OUT

i = Output voltage of the i channel

•I

LOAD

i = Load current of the i channel

By setting the two P

DMAX

equations equal to each other, we

can solve for the R

LOAD

s to avoid the device overheat. The

package power dissipation curves provide a convenient way

to see if the device will overheat.

THERMAL SHUTDOWN

The EL5625 has an internal thermal shutdown circuitry that

prevents overheating of the part. When the junction

temperature goes up to about 150°C, the part will be

disabled. When the junction temperature drops down to

about 120°C, the part will be enabled. With this feature, any

short circuit at the outputs will enable the thermal shutdown

circuitry to disable the part.

POWER SUPPLY BYPASSING AND PRINTED CIRCUIT

BOARD LAYOUT

Good printed circuit board layout is necessary for optimum

performance. A low impedance and clean analog ground

plane should be used for the EL5625. The traces from the

two ground pins to the ground plane must be very short. The

thermal pad of the EL5625 should be connected to the

analog ground plane. Lead length should be as short as

possible and all power supply pins must be well bypassed. A

0.1µF ceramic capacitor must be place very close to the V

REFH

, V

REFL

, and CAP pins. A 4.7µF local bypass

tantalum capacitor should be placed to the V

, V

REFH

, and

REFL

pins.

DMAX

JMAX

- T

AMAX



---------------------------------------------

DMAX

 V

 - V

OUT

i  I

LOAD

i+=

DMAX

 V

OUT

LOAD

i+=

EL5625

FN7488.1

February 20, 2008

EL5625

QFN (Quad Flat No-Lead) Package Family

PIN #1

I.D. MARK

(N-2)

(N-1)

(N/2)

0.075

TOP VIEW

(N/2)

PIN #1 I.D.

(N-2)

(N-1)

N LEADS

BOTTOM VIEW

DETAIL X

PLANE

SEATING

N LEADS

SEE DETAIL "X"

(L)

N LEADS

& EXPOSED PAD

0.10

SIDE VIEW

0.10 BA

0.075 C

(E2)

(D2)

0.08 C

(c)

MDP0046

QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY

(COMPLIANT TO JEDEC MO-220)

SYMBOL

MILLIMETERS

TOLERANCE NOTESQFN44 QFN38 QFN32

A 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -

b 0.25 0.25 0.23 0.22 ±0.02 -

c 0.20 0.20 0.20 0.20 Reference -

D 7.00 5.00 8.00 5.00 Basic -

D2 5.10 3.80 5.80 3.60/2.48 Reference 8

E 7.00 7.00 8.00 6.00 Basic -

E2 5.10 5.80 5.80 4.60/3.40 Reference 8

e 0.50 0.50 0.80 0.50 Basic -

L 0.55 0.40 0.53 0.50 ±0.05 -

N 44 38 32 32 Reference 4

ND 11 7 8 7 Reference 6

NE 11 12 8 9 Reference 5

SYMBOL

MILLIMETERS

TOLER-

ANCE NOTESQFN28 QFN24 QFN20 QFN16

A 0.90 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 0.02 +0.03/

-0.02

b 0.25 0.25 0.30 0.25 0.33 ±0.02 -

c 0.20 0.20 0.20 0.20 0.20 Reference -

D 4.00 4.00 5.00 4.00 4.00 Basic -

D2 2.65 2.80 3.70 2.70 2.40 Reference -

E 5.00 5.00 5.00 4.00 4.00 Basic -

E2 3.65 3.80 3.70 2.70 2.40 Reference -

e 0.50 0.50 0.65 0.50 0.65 Basic -

L 0.40 0.40 0.40 0.40 0.60 ±0.05 -

N 28 24 20 20 16 Reference 4

ND 6 5 5 5 4 Reference 6

NE 8 7 5 5 4 Reference 5

Rev 11 2/07

NOTES:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Tiebar view shown is a non-functional feature.

3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.

4. N is the total number of terminals on the device.

5. NE is the number of terminals on the “E” side of the package

(or Y-direction).

6. ND is the number of terminals on the “D” side of the package

(or X-direction). ND = (N/2)-NE.

7. Inward end of terminal may be square or circular in shape with radius

(b/2) as shown.

8. If two values are listed, multiple exposed pad options are available.

Refer to device-specific datasheet.

P1-P3 P4-P6 P7-P9 P10-P12

EL5625ILZ-T13

Mfr. #:

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Manufacturer:

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Description:

LCD Gamma Buffers EL5625ILZ PROGUFR + VCOM

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EL5625ILZ-T13

EL5625ILZ-T13

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