8
FN7488.1
February 20, 2008
Serial Timing Diagram
V
COM
Amplifier
The V
COM
amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rates for the display. Thus
the amplifier must be capable of sourcing and sinking
capacitive pulse of current, which can be quite large (100mA
for typical applications).
Analog Section
TRANSFER FUNCTION
The transfer function is:
where data is the decimal value of the 11-bit data binary
input code.
The output voltages from the EL5625 will be derived from
the reference voltages present at the V
REFL
and V
REFH
pins. The impedance between those two pins is about 32k.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5625. GND < V
REFH
V
S
and GND V
REFL
V
REFH
.
CLOCK OSCILLATOR
The EL5625 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labelled EXT_OSC. The internal clock is
provided by an internal oscillator running at approximately
21kHz and can be output to the EXT_OSC pin. In a 2 chip
system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin will
output the clock from the internal oscillator. The second chip
may have the OSC pin connected to this clock source.
For transient load application, the external clock mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
TABLE 2. SERIAL TIMING PARAMETERS
PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION
T 200ns Clock Period
t
r
/t
f
0.05 * T Clock Rise/Fall Time
t
HE
10ns ENA Hold Time
t
SE
10ns ENA Setup Time
t
HD
10ns Data Hold Time
t
SD
10ns Data Setup Time
t
W
0.50 * T Clock Pulse Width
B15 B14 B13 B12-B2 B1 B0
ENA
SCLK
SDI
MSB LSB
t
t
HE
t
SE
t
SD
t
HD
Tt
r
t
w
t
HE
t
SE
LOAD MSB FIRST, LSB LAST
t
f
V
OUT IDEAL
V
REFL
=
data
2048
-------------
V
REFH
- V
REFL
+
EL5625
