12
UDC RAM and UDC Address Register
Figure 3 shows the logic levels needed to access the UDC
RAM and the UDC Address Register. The UDC Address
Register is eight bits wide. The lower four bits (D
0
-D
3
) are
used to select one of the 16 UDC locations. The upper
four bits (D
4
-D
7
) are not used. Once the UDC address has
been stored in the UDC Address Register, the UDC RAM
can be accessed.
To completely specify a 5 x 7 character, eight write cycles
are required. One cycle is used to store the UDC RAM
address in the UDC Address Register and seven cycles are
used to store dot data in the UDC RAM. Data is entered by
rows and one cycle is needed to access each row. Figure 4
shows the organization of a UDC character assuming the
symbol to be stored is an “F.” A
0
-A
2
are used to select the
row to be accessed and D
0
-D
4
are used to transmit the
row dot data. The upper three bits (D
5
-D
7
) are ignored.
D
0
(least signi cant bit) corresponds to the right most
column of the 5 x 7 matrix and D
4
(most signicant bit)
corresponds to the left most column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels needed to access the
Flash RAM. The Flash RAM has one bit associated with
each location of the Character RAM. The Flash input is
used to select the Flash RAM while address lines A
3
-A
4
are ignored. Address lines A
0
-A
2
are used to select the
loca tion in the Flash RAM to store the attri bute. D
0
is used
to store or remove the ash attribute. D
0
= “1” stores the
attribute and D
0
= “0” removes the attribute.
When the attribute is enabled through bit 3 of the
Control Word and a “1” is stored in the Flash RAM, the
corresponding character will ash at approxi mately 2
Hz. The actual rate is dependent on the clock fre quency.
For an external clock the ash rate can be calculated by
dividing the clock frequency by 28,672.
Figure 4. Data to load “”F’’ into the UDC RAM.
Figure 3. Logic levels to access a UDC character.
CE
FL A
4
A
3
A
2
A
1
A
0
RST WR RD
01
00
01
1
001XXX
0
11
UNDEFINED
CONTROL SIGNALS
UDC ADDRESS REGISTER ADDRESS
UDC ADDRESS REGISTER DATA FORMAT
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
000 = ROW 1
110 = ROW 7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X UDC CODE
XXX
FL A
4
A
3
A
2
A
1
A
0
011 ROW SELECT
UDC RAM ADDRESS
UDC RAM C C
DATA FORMAT O O
L L
1 5
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X DOT DATA
XX
CERST WR RD
01
00
01
10
11
UNDEFINED
CONTROL SIGNALS
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
C C C C C
O O O O O
L L L L L
1 2 3 4 5
D
4
D
3
D
2
D
1
D
0
UDC CHARACTER HEX CODE
1 1 1 1 1 ROW 1 • • • • • 1F
1 0 0 0 0 ROW 2 • 10
1 0 0 0 0 ROW 3 • 10
1 1 1 1 0 ROW 4 • • • • 1D
1 0 0 0 0 ROW 5 • 10
1 0 0 0 0 ROW 6 • 10
1 0 0 0 0 ROW 7 • 10
IGNORED
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
