25LC512
DS20005265A-page 4 2014 Microchip Technology Inc.
TABLE 1-3: AC TEST CONDITIONS
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
AC Waveform:
VLO = 0.2V
V
HI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 30 pF
Timing Measurement Reference Level
Input 0.5 V
CC
Output 0.5 VCC
Note 1: For VCC 4.0V
2: For V
CC > 4.0V
CS
SCK
SO
SI
HOLD
1716 16 17
1918
Don’t Care
5
High-Impedance
n + 1 n n - 1n
nn - 1
1716 1716
1918
High-Impedance
n - 2
n + 1 n n - 2
Don’t Care
CS
SCK
SI
SO
65
8
7
11
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
2014 Microchip Technology Inc. DS20005265A-page 5
25LC512
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
10
9
13
MSB out
LSB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
25LC512
DS20005265A-page 6 2014 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25LC512 is a 65,536 byte Serial EEPROM
designed to interface directly with the Serial Periph-
eral Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25LC512 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
pin must
be low and the HOLD
pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS
goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LC512 in ‘HOLD’
mode. After releasing the HOLD
pin, operation will
resume from the point when the HOLD
was asserted.
BLOCK DIAGRAM
TABLE 2-1: INSTRUCTION SET
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
PE 0100 0010 Page Erase – erase one page in memory array
SE 1101 1000 Sector Erase – erase one sector in memory array
CE 1100 0111 Chip Erase – erase all sectors in memory array
RDID 1010 1011 Release from Deep power-down and read electronic signature
DPD 1011 1001 Deep Power-Down mode

25LC512-M/SN

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM Serial EEPROM 512K 64K X 8, 2.5V MIL T
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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