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SP526CF-L

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
16
Rev: C Date:2/1/06 SP526 Multi–Mode Serial Transceiver © Copyright 2006 Sipex Corporation
-
of the ITU V.10 specification. The RS-423
drivers are used in RS-449, EIA-530, EIA-530A
and V.36 modes as Category II signals from
each of their corresponding specifications.
The third and fourth type of drivers are RS-422
(V.11)/RS-485 type differential drivers. Due to
the nature of differential signaling, the drivers
are more immune to noise as opposed to single-
ended transmission methods. The advantage is
evident over high speeds and long transmission
lines. The strength of the driver outputs can
produce differential signals that can maintain
RS-485, ±1.5V differential output levels with a
worst case load of 54Ω. The signal levels and
drive capability of these drivers allow the driv-
ers to also support RS-422 (V.11) requirements
of ±2V differential output levels with 100Ω
loads. The driver is designed to operate over a
common mode range of +7V to -7V which
follows the V.11 specification. The RS-422
drivers are used in RS-449, EIA-530, EIA-530A
and V.36 modes as Category I signals which are
used for clock and data. All of the differential
drivers can operate to at least 10Mbps.
The drivers also have separate enable pins which
simplifies half-duplex configurations for some
applications and also provides simpler DTE/
DCE flexibility with one integrated circuit. The
enable pins will tri-state the drivers when the
ENT1, ENT2, ENT3, and ENT4 pins are at a
logic HIGH ("1"). During tri-stated conditions,
the driver outputs will be at a high impedance
state.
The driver inputs are both TTL or CMOS com-
patible. Each driver input should have a pull-
down or pull-up resistor so that the output will
be at a defined state. Unused driver inputs
should have pull-up resistors to +5V connected
so that the output is at a logic LOW ("0").
Unused driver inputs should not be left floating.
For differential drivers, the non-inverting out-
put will be at a logic HIGH ("1"). The typical
pull-up resistor value should be 400kΩ.
Receivers
The SP526 has four independent receivers which
can be programmed for the different interface
modes. Control for the mode selection is done
via a two–bit control word that is the same as the
driver control word. Therefore, if the modes for
the drivers and receivers are supposed to be
identical in the application, the control lines can
be tied together.
Like the drivers, the receivers are prearranged
for the specific requirements of the synchronous
serial interface. As the operating mode of the
receivers is changed, the electrical characteris-
tics will change to support the required serial
interface protocols of the receivers. Table 1
shows the mode of each receiver in the different
interface modes that can be selected.
There are two basic types of receiver circuits —
RS-232 (V.28) and RS-422 (V.11).
The RS-232 (V.28) receiver is single–ended and
accepts RS-232 signals from the RS-232 driver.
The RS-232 receiver has an operating voltage
range of ±15V and can receive signals downs to
±3V. The input sensitivity complies with RS-
232 and V.28 at ±3V. The input impedance is
3kΩ to 7kΩ in accordance to RS-232 and V.28.
The receiver output produces a TTL/CMOS
signal with a +2.4V minimum for a logic "1" and
a +0.8V maximum for a logic "0". RS-232(V.28)
receivers can be used in RS-232 mode for data,
clock or control signals. They are also used in
V.35 mode for control line signals: CTS, DSR,
LL, and RL. The RS-232 receivers can operate
to at least 120kbps.
17
Rev: C Date:2/1/06 SP526 Multi–Mode Serial Transceiver © Copyright 2006 Sipex Corporation
The third type of receiver is a differential which
supports RS-422/V.11 signals. This receiver
has a typical input impedance of 10KΩ and a
differential threshold of ±0.3V, which complies
with the RS-422/V.11 specifications. Since the
characteristics of the RS-422 (V.11) receivers
are actually subsets of RS-485, the RS-422/
V.11 receivers can accept RS-485 signals.
However, these receivers cannot support 32
transceivers on the signal bus due to the lower
input impedance as specified in the RS-485
specifications. V.11 receivers are used in
RS-422, RS-449, EIA-530, EIA-530A and V.36
as Category I signals for receiving clock, data,
and some control line signals not covered
by Category II V.10 circuits. The differential
receivers can receive signals up to at least
10Mbps.
All four receivers include an enable line for
tri-state of the receiver output allowing
convenient half-duplex configurations. When
the enable lines are at a logic LOW ("0") active,
the receiver outputs are high impedance and will
be at approximately 10kΩ during tri-state.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open. For single-ended RS-232 receivers, there
are internal 5kΩ pull-down resistors on the
inputs which produces a logic high ("1") at the
receiver outputs. The single-ended RS-423
receivers produce a logic LOW ("0") on the
output when the inputs are open. This is due to
a pull-up device connected to the input. The
differential receivers have the same internal
pull-up device on the non-inverting input which
produces a logic HIGH ("1") at the receiver output.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external capaci-
tors, but uses a four–phase voltage shifting
technique to attain symmetrical 10V power
supplies. There is a free–running oscillator that
controls the four phases of the voltage shifting.
A description of each phase follows.
Phase 1
— V
SS
charge storage —During this phase of
the clock cycle, the positive side of capacitors
C
1
and C
2
are initially charged to +5V. C
l
+
is
then switched to ground and the charge in C
1
–
is
transferred to C
2
–
. Since C
2
+
is connected to
+5V, the voltage potential across capacitor C
2
is
now 10V.
Phase 2
— V
SS
transfer — Phase two of the clock
connects the negative terminal of C
2
to the V
SS
storage capacitor and the positive terminal of C
2
to ground, and transfers the generated –l0V to
C
3
. Simultaneously, the positive side of
capacitor C
1
is switched to +5V and the
negative side is connected to ground.
Phase 3
— V
DD
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
1
produces –5V in the negative
terminal of C
1
, which is applied to the negative
side of capacitor C
2
. Since C
2
+
is at +5V, the
voltage potential across C
2
is l0V.
C
1
+
-
-5V
V
CC
= +5V
+5V
C
2
-5V
C
4
C
3
+
-
+
-
-
+
V
DD
Storage Capacitor
V
SS
Storage Capacitor
Figure 30. Charge Pump — Phase 1
18
Rev: C Date:2/1/06 SP526 Multi–Mode Serial Transceiver © Copyright 2006 Sipex Corporation
-
Figure 31. Charge Pump — Phase 2
C
1
+
-
V
CC
= +5V
C
2
-10V
C
4
C
3
+
-
+
-
-
+
V
DD
Storage Capacitor
V
SS
Storage Capacitor
Figure 32. Charge Pump Waveforms
+10V
a) C
2
+
GND
GND
b) C
2
–
–10V
Figure 33. Charge Pump — Phase 3
C
1
+
-
-5V
V
CC
= +5V
+5V
C
2
-5V
C
4
C
3
+
-
+
-
-
+
V
DD
Storage Capacitor
V
SS
Storage Capacitor
Figure 34. Charge Pump — Phase 4
C
1
+
-
V
CC
= +5V
+10V
C
2
C
4
C
3
+
-
+
-
-
+
V
DD
Storage Capacitor
V
SS
Storage Capacitor
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

SP526CF-L

Mfr. #:
Buy SP526CF-L
Manufacturer:
MaxLinear
Description:
IC TXRX WAN MULTI-MODE 44LQFP
Lifecycle:
New from this manufacturer.
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