10
LT1737
1737fa
OPERATIO
U
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to finite rise
time on the MOSFET drain node, but more importantly,
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side not directly related to
output voltage. (Some time is also required for internal
settling of the feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turnoff command
and the enabling of the feedback amplifier. This is termed
enable delay. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Application Infor-
mation for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of V
BG
. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V
C
node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information for details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V
C
node slew rate.
LOAD COMPENSATION THEORY
The LT1737 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
T1
M1
R3
50k
V
IN
R2
LOAD
COMP I
R1
FB
V
BG
Q1 Q2
I
M
I
M
R
OCMP
R
CMPC
R
SENSE
I
SENSE
1737 F01
Q3
+
A1
Figure 1. Load Compensation Diagram
11
LT1737
1737fa
transformer secondary and output capacitor. This has
been represented previously by the expression “I
SEC
ESR.” However, it is generally more useful to convert this
expression to an effective output impedance. Because the
secondary current only flows during the off portion of the
duty cycle, the effective output impedance equals the
lumped secondary impedance times the inverse of the OFF
duty cycle. That is:
R ESR
DC
OUT
OFF
=
1
where
R
OUT
= effective supply output impedance
ESR = lumped secondary impedance
DC
OFF
= OFF duty cycle
Expressing this in terms of the ON duty cycle, remember-
ing DC
OFF
= 1 – DC,
R ESR
DC
OUT
=
1
1–
DC = ON duty cycle
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external FB resistor
divider adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error may be minimized by the use of the load compensa-
tion function.
To implement the load compensation function, a voltage is
developed that is proportional to average output switch
current. This voltage is then impressed across the external
R
OCMP
resistor, and the resulting current acts to decrease
the voltage at the FB pin. As output loading increases,
average switch current increases to maintain rough output
voltage regulation. This causes an increase in R
OCMP
resistor current which effects a corresponding increase in
flyback voltage amplitude.
Assuming a relatively fixed power supply efficiency, Eff,
Power Out = Eff • Power In
V
OUT
• I
OUT
= Eff • V
IN
• I
IN
Average primary side current may be expressed in terms
of output current as follows:
OPERATIO
U
I
V
V Eff
I
IN
OUT
IN
OUT
=
combining the efficiency and voltage terms in a single
variable:
I
IN
= K1 • I
OUT
, where
K
V
V Eff
OUT
IN
1=
Switch current is converted to voltage by the external
sense resistor and averaged/lowpass filtered by R3 and
the external capacitor on R
CMPC
. This voltage is then
impressed across the external R
OCMP
resistor by op amp
A1 and transistor Q3. This produces a current at the
collector of Q3 which is then mirrored around and then
subtracted from the FB node. This action effectively in-
creases the voltage required at the top of the R1/R2
feedback divider to achieve equilibrium. So the effective
change in V
OUT
target is:
=
()
=
VKI
R
R
RRor
V
I
K
R
R
RR
OUT OUT
SENSE
OCMP
OUT
OUT
SENSE
OCMP
112
112
••(||)
( || )
Nominal output impedance cancellation is obtained by
equating this expression with R
OUT
:
RK
R
R
R R and
RK
R
R
R R where
OUT
SENSE
OCMP
OCMP
SENSE
OUT
=
=
112
112
( || )
( || )
K1 = dimensionless variable related to V
IN
, V
OUT
and
efficiency as above
R
SENSE
= external sense resistor
R
OUT
= uncompensated output impedance
(R1||R2) = impedance of R1 and R2 in parallel
The practical aspects of applying this equation to deter-
mine an appropriate value for the R
OCMP
resistor are found
in the Applications Information section.
12
LT1737
1737fa
APPLICATIO S I FOR ATIO
WUUU
TRANSFORMER DESIGN CONSIDERATIONS
Transformer specification and design is perhaps the most
critical part of applying the LT1737 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Turns Ratios
Note that due to the use of the external feedback resistor
divider ratio to set output voltage, the user has relative
freedom in selecting transformer turns ratio to suit a given
application. In other words, “screwball” turns ratios like
“1.736:1.0” can scrupulously be avoided! In contrast,
simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can
be employed which yield more freedom in setting total
turns and mutual inductance. Turns ratio can then be
chosen on the basis of desired duty cycle. However,
remember that the input supply voltage plus the second-
ary-to-primary referred version of the flyback pulse (in-
cluding leakage spike) must not exceed the allowed external
MOSFET breakdown rating.
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after output switch turnoff. This
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In many cases a
“snubber” circuit will be required to avoid overvoltage
breakdown at the output switch node. Application Note
AN19 is a good reference on snubber design.
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node, and this works to
the user’s advantage in rejecting large, i.e., higher voltage,
leakage spikes. In other words, once a leakage spike is
several volts in amplitude, a further increase in amplitude
has little effect on the feedback system. So the user is
generally advised to arrange the snubber circuit to clamp
at as high a voltage as comfortably possible, observing
MOSFET breakdown, such that leakage spike duration is
as short as possible.
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the V
SW
waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note—the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,

LT1737IGN#TRPBF

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Analog Devices / Linear Technology
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Switching Voltage Regulators Hi Pwr Iso Fly Cntr
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