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LT1737
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APPLICATIO S I FOR ATIO
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which reduces the size of the primary-referred flyback
pulse used for feedback. This will increase the output
voltage target by a similar percentage. Note that unlike
leakage
spike
behavior, this phenomena is load indepen-
dent. To the extent that the secondary leakage inductance
is a constant percentage of mutual inductance (over
manufacturing variations), this can be accommodated by
adjusting the feedback resistor divider ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (P
OUT
/P
IN
). Resistance in the
secondary increases effective output impedance which
degrades load regulation, (at least before load compensa-
tion is employed).
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However, re-
member that this will increase primary-to-secondary ca-
pacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
SELECTING FEEDBACK RESISTOR DIVIDER VALUES
The expression for V
OUT
developed in the Operation sec-
tion can be rearranged to yield the following expression for
the R1/R2 ratio:
RR
R
V V I ESR
V
N
OUT F SEC
BG
ST
12
2
+
()
=
++
()
where:
V
OUT
= desired output voltage
V
F
= switching diode forward voltage
I
SEC
• ESR = secondary resistive losses
V
BG
= data sheet reference voltage value
N
ST
= effective secondary-to-third winding turns ratio
The above equation defines only the ratio of R1 to R2, not
their individual values. However, a “second equation for
two unknowns” is obtained from noting that the Thevenin
impedance of the resistor divider should be roughly 3k for
bias current cancellation and other reasons.
SELECTING R
OCMP
RESISTOR VALUE
The Operation section previously derived the following
expressions for R
OUT
, i.e., effective output impedance and
R
OCMP
, the external resistor value required for its nominal
compensation:
R ESR
DC
RK
R
R
RR
OUT
OCMP
SENSE
OUT
=
=
()
1
1
112
||
While the value for R
OCMP
may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of V
IN
to
V
OUT
times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
Build a prototype of the desired supply using the eventual
secondary components. Temporarily ground the R
CMPC
pin to disable the load compensation function. Operate the
supply over the expected range of output current loading
while measuring the output voltage deviation. Approxi-
mate this variation as a single value of R
OUT
(straight line
approximation). Calculate a value for the K1 constant
based on V
IN
, V
OUT
and the measured (differential) effi-
ciency. These are then combined with R
SENSE
as indicated
to yield a value for R
OCMP
.
Verify this result by connecting a resistor of roughly this
value from the R
OCMP
pin to ground. (Disconnect the
ground short to R
CMPC
and connect the requisite 0.1µF
filter capacitor to ground.) Measure the output impedance
with the new compensation in place. Modify the original
R
OCMP
value if necessary to increase or decrease the
effective compensation.
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LT1737
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SELECTING OSCILLATOR CAPACITOR VALUE
The switching frequency of the LT1737 is set by an
external capacitor connected between the OSCAP pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 2 shows the nominal relationship between
external capacitance and switching frequency. To mini-
mize stray capacitance and potential noise pickup, this
capacitor should be placed as close as possible to the IC
and the OSCAP node length/area minimized.
APPLICATIO S I FOR ATIO
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indicative of actual current level in the transformer pri-
mary, and may cause irregular current mode switching
action, especially at light load.
However, the user must remember that the LT1737 does
not “skip cycles” at light loads. Therefore, minimum on
time will set a limit on minimum delivered power and con-
sequently a minimum load requirement to maintain regu-
lation (see Minimum Load Considerations). Similarly,
minimum on time has a direct effect on short-circuit be-
havior (see Maximum Load/Short-Circuit Considerations).
The user is normally tempted to set the minimum on time
to be short to minimize these load related consequences.
(After all, a smaller minimum on time approaches the ideal
case of zero, or no minimum.) However, a longer time may
be required in certain applications based on MOSFET
switching current spike considerations.
Enable Delay Time
This function provides a programmed delay between
turnoff of the gate drive node and the subsequent enabling
of the feedback amplifier. At high loads, a primary side
voltage spike after MOSFET turnoff may be observed due
to transformer leakage inductance. This spike is not in-
dicative of actual output voltage (see Figure 4B). Delaying
the enabling of the feedback amplifier allows this system
to effectively ignore most or all of the voltage spike and
maintain proper output voltage regulation. The enable
delay time should therefore be set to the maximum ex-
pected duration of the leakage spike. This may have
C
OSCAP
(pF)
30
50
f
OSC
(Hz)
100
300
100 200
1737 F02
Figure 2. f
OSC
vs OSCAP Value
SELECTING TIMING RESISTOR VALUES
There are three internal “one-shot” times that are pro-
grammed by external application resistors: minimum on
time, enable delay time and minimum enable time. These
are all part of the isolated flyback control technique, and
their functions have been previously outlined in the Opera-
tion section. Figure 3 shows nominal observed time ver-
sus external resistor value for these functions.
The following information should help in selecting and/or
optimizing these timing values.
Minimum On Time
This time defines a period whereby the normal switch
current limit is ignored. This feature provides immunity to
the leading edge current spike often seen at the source
node of the external power MOSFET, due to rapid charging
of its gate/source capacitance. This current spike is not
R
T
(k)
20
100
500
TIME (ns)
1000
100 250
1737 F03
Figure 3. “One Shot” Times vs Programming Resistor
15
LT1737
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implications regarding output voltage regulation at mini-
mum load (see Minimum Load Considerations).
A second benefit of the enable delay time function occurs
at light load. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage (see Figure 4C). So
the enable delay time should also be set long enough to
ignore the “irrelevant” portion of the flyback waveform at
light load.
Additionally, there are cases wherein the gate output is
called upon to drive a large geometry MOSFET such that
the turnoff transition is slowed significantly. Under such
circumstances, the enable delay time may be increased to
accommodate for the lengthy transition.
Average “start-up” V
C
current =
MinimumEnable Time
SwitchingFrequency
I
SRC
Minimum enable time can also have implications at light
load (see Minimum Load Considerations). The temptation
is to set the minimum enable time to be fairly short, as this
is the least restrictive in terms of minimum load behavior.
However, to provide a “reliable” minimum start-up current
of say, nominally 1µA, the user should set the minimum
enable time at no less that 2% of the switching period
(= 1/switching frequency).
CURRENT SENSE RESISTOR CONSIDERATIONS
The external current sense resistor allows the user to
optimize the current limit behavior for the particular appli-
cation under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak switch current goes from a fraction of an ampere to
tens of amperes. Care must be taken to ensure proper
circuit operation, especially with small current sense
resistor values.
For example, a peak switch current of 10A requires a
sense resistor of 0.025. Note that the instantaneous
peak power in the sense resistor is 2.5W, and it must be
rated accordingly. The LT1737 has only a single sense line
to this resistor. Therefore, any parasitic resistance in the
ground side connection of the sense resistor will increase
its apparent value. In the case of a 0.025 sense resistor,
one milliohm
of parasitic resistance will cause a 4%
reduction in peak switch current. So resistance of printed
circuit copper traces and vias cannot necessarily be
ignored.
An additional consideration is parasitic inductance. In-
ductance in series with the current sense resistor will
accentuate the high frequency components of the current
waveform. In particular, the gate switching spike and
multimegahertz ringing at the MOSFET can be
considerably amplified. If severe enough, this can cause
erratic operation. For example, assume 3nH of parasitic
inductance (equivalent to about 0.1 inch of wire in free
space) is in series with an ideal 0.025 sense resistor.
A “zero” will be formed at f = R/(2πL), or 1.3MHz. Above
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ENABLE DELAY
TIME NEEDED
1737 F04
DISCONTINUOUS
MODE
RINGING
IDEALIZED FLYBACK
WAVEFORM
MOSFET GATE DRIVE
FLYBACK WAVEFORM
WITH LARGE LEAKAGE
SPIKE AT HEAVY LOAD
“SLOW” FLYBACK
WAVEFORM AT
LIGHT LOAD
B
A
C
ENABLE
DELAY
TIME
NEEDED
Figure 4
Minimum Enable Time
This function sets a minimum duration for the expected
flyback pulse. Its primary purpose is to provide a mini-
mum source current at the V
C
node to avoid start-up
problems.

LT1737IGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr Iso Fly Cntr
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