7
FN6494.0
April 25, 2008
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once
the rising VCC voltage exceeds 3.8V (typically), operation of
the driver is enabled and the PWM input signal takes control
of the gate drives. If VCC drops below the falling threshold of
3.5V (typically), operation of the driver is disabled.
Internal Bootstrap Device
ISL6620, ISL6620A features an internal bootstrap Schottky
diode. Simply adding an external capacitor across the BOOT
and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing
at the trailing-edge of the PHASE node. This reduces
voltage stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for VCC. Its
capacitance value can be estimated using Equation 1:
where Q
G1
is the amount of gate charge per upper MOSFET
at V
GS1
gate-source voltage and N
Q1
is the number of
control MOSFETs. The ΔV
BOOT_CAP
term is defined as the
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 2.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
SW
), the output drive impedance, the
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (Q
G
). Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal impedance
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated using Equations 2 and 3, respectively:
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET data sheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
Q*
VCC
product is the quiescent power of the driver without a load.
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R
G1
and R
G2
) and the internal gate
resistors (R
GI1
and R
GI2
) of MOSFETs. Figures 3 and 4 show
the typical upper and lower gate drives turn-on current paths.
20nC
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
ΔV
BOOT_CAP
(V)
C
BOOT_CAP
(µF)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
Q
GATE
= 100nC
50nC
C
BOOT_CAP
Q
GATE
ΔV
BOOT_CAP
--------------------------------------
Q
GATE
Q
G1
VCC
V
GS1
-------------------------------
N
Q1
=
(EQ. 1)
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC++=
(EQ. 2)
P
Qg_Q1
Q
G1
UVCC
2
V
GS1
---------------------------------------
F
SW
N
Q1
=
P
Qg_Q2
Q
G2
LVCC
2
V
GS2
--------------------------------------
F
SW
N
Q2
=
I
DR
Q
G1
UVCC N
Q1
V
GS1
------------------------------------------------------
Q
G2
LVCC N
Q2
V
GS2
-----------------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
F
SW
I
Q
+=
(EQ. 3)
P
DR
P
DR_UP
P
DR_LOW
I
Q
VCC++=
(EQ. 4)
P
DR_UP
R
HI1
R
HI1
R
EXT1
+
--------------------------------------
R
LO1
R
LO1
R
EXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q1
2
---------------------
=
P
DR_LOW
R
HI2
R
HI2
R
EXT2
+
--------------------------------------
R
LO2
R
LO2
R
EXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q2
2
---------------------
=
R
EXT1
R
G1
R
GI1
N
Q1
-------------
+= R
EXT2
R
G2
R
GI2
N
Q2
-------------
+=
Q1
D
S
G
R
G1R
L1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
UVCC
ISL6620, ISL6620A
8
FN6494.0
April 25, 2008
Application Information
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding the device’s absolute
maximum ratings. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging, as well as the
driver can minimize such unwanted stress.
The selection of D
2
-PAK, or D-PAK packaged MOSFETs, is
a much better match (for the reasons discussed) for the
ISL6620A. Low-profile MOSFETs, such as Direct FETs and
multi-source leads devices (SO-8, LFPAK, PowerPAK), have
low parasitic lead inductances and can be driven by either
ISL6620 or ISL6620A (assuming proper layout design). The
ISL6620, missing the 3Ω integrated BOOT resistor, typically
yields slightly higher efficiency than the ISL6620A.
Layout Considerations
FA good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
optimized layout:
Keep decoupling loops (VCC-GND and BOOT-PHASE) as
short as possible.
Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
VCC) should be short and wide, as much as possible.
Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
In addition, connecting the thermal pad of the DFN package
to the power ground through a via, or placing a low noise
copper plane underneath the SOIC part is recommended for
high switching frequency, high current applications. This is to
improve heat dissipation and allow the part to achieve its
full thermal potential.
Upper MOSFET Self Turn-on Effects at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
coupling via the internal C
GD
of the MOSFET, the gate of the
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
place a resistor (R
UGPH
) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
GD
/C
GS
ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C
DS
/C
GS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated using Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 5 provides a visual reference for this
phenomenon and its potential solution.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
LVCC
Q2
D
S
G
R
G2R
L2
R
HI2
C
DS
C
GS
C
GD
R
LO2
V
GS_MILLER
dV
dt
-------
RC
rss
1e
V
DS
dV
dt
-------
RC
iss
----------------------------------
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎜⎟
⎛⎞
⋅⋅=
RR
UGPH
R
GI
+=
C
rss
C
GD
=
C
iss
C
GD
C
GS
+=
(EQ. 5)
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
GI
R
UGPH
BOOT
DU
C
DS
C
GS
C
GD
DL
PHASE
UVCC
ISL6620, ISL6620A
C
BOOT
UGATE
ISL6620, ISL6620A
9
FN6494.0
April 25, 2008
ISL6620, ISL6620A
Dual Flat No-Lead Plastic Package (DFN)
D
E
A
B
0.10 MC
e
0.415
C
SECTION "C-C"
NX (b)
(A1)
2X
C
0.15
0.15
2X
B
NX L
REF.
(Nd-1)Xe
5
A
C
(DATUM B)
D2
D2/2
E2
E2/2
TOP VIEW
7
BOTTOM VIEW
5
6
INDEX
AREA
8
AB
NX
k
6
INDEX
AREA
(DATUM A)
12
N-1N
NX b
8
NX b
NX L
0.200
C
A
SEATING
PLANE
0.08
C
A3
SIDE VIEW
0.10 C
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.23 0.28 5,8
D 3.00 BSC -
D2 1.95 2.00 2.05 7,8
E 3.00 BSC -
E2 1.55 1.60 1.65 7,8
e 0.50 BSC -
k0.25 - - -
L0.300.35 0.40 8
N102
Nd 5 3
Rev. 3 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
FOR ODD TERMINAL/SIDE
C
L
e
TERMINAL TIP
L
CC

ISL6620AIRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers SYNCH BUCK MSFT 5V DRVR3OHM R BOOT VR11
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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