[AK4121A]
MS0337-E-06 2010/04
- 10 -
Figure 5. 16bit/20bit LSB justified Timing
Figure 6. 20bit MSB justified Timing
Figure 7. 20bit I
2
S Timing
SDTI
LRCK
BICK
(
64fs
)
0 13 1 14 15 16 31 0 1 13 14 15 16 31 0 1
15 0
15 0
16bi
Don’t care Don’t care
15:MSB, 0:LSB
SDTI
20bi
19:MSB, 0:LSB
16 15 0
16 15 0
Dont care
Don’t care
17 17
12 12
18 18
Lch Data Rch Data
19 19
LRCK
BICK
(
64fs
)
SDTI
0 18 1 2 20 31 0 1 31 0 1
20:MSB, 0:LSB
18 1 0 Dont care 19
Lch Data Rch Data
19 30 1822019 30
18 1 0 Don’t care 19
1819
LRCK
BICK
(
64fs
)
SDTI
0 3 1 2 20 31 0 1 31 0 1
19:MSB, 0:LSB
18
1
0
Don’t care 19
Lch Data Rch Data
19 21 322019 21
18 1 0 Dont care 19 19
[AK4121A]
MS0337-E-06 2010/04
- 11 -
Soft Mute Operation
When the SMUTE pin changes to “H”, the output signal is attenuated from 0dB to
dB during 1024 OLRCK cycles.
When the SMUTE pin returns to “L”, the attenuation is cancelled and the output signal gradually changes to 0dB during
1024 OLRCK cycles. If the soft mute is cancelled before attenuating to
, the attenuation is discontinued and returns
to 0dB by the same cycles. The soft mute is effective for changing the signal source.
Notes:
(1) Transition time. 1024 OLRCK cycles (1024/fso).
(2) If the soft mute is cancelled before attenuating to
after starting the operation, the attenuation is discontinued
and returned to 0dB by the same number of clock cycles.
Figure 8. Soft Mute
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15µs) and is enabled or disabled
with DEM0 and DEM1.
Mode DEM1 DEM0 De-emphasis filter
0 L L 44.1kHz
1 L H OFF
2 H L 48kHz
3 H H 32kHz
Table 4. De-emphasis Filter Control
SMUTE
0dB
Attenuation Level
at SDTO
-
dB
(1)
(2)
(1)
[AK4121A]
MS0337-E-06 2010/04
- 12 -
System Reset
Bringing the PDN pin=“L” places the AK4121A in the power-down mode and initializes the digital filter. This reset
should always be done after power-up. When the PDN pin = “L”, the SDTO output is “L”. Regarding the SDTO valid
time, please refer to the
Table 5. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
Case 2
t
a
External clocks
(input port)
SDTI
don’t care
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
t
b
normal data
(state1)
External clocks
(output port)
don’t care
don’t care
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
normal
operation
PLL lock &
fs detection
(1)
normal data
PD
(state1)
(state1)
(state2)
(state2)
(state2)
“0” data
“0” data
External clocks
(input port)
SDTI
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
(1)
normal data
(no clock)
External clocks
(output port)
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
PLL
Unlock
(state1)
(state1)
(state1)
“0” data
(don’t care)
(don’t care)
Note:
(1) <100ms for recommended value 2, <200ms for recommended value 1. (
Figure 11)
Figure 9. System Reset
Reset time
t
a
Data valid time
t
b
10ms
<100ms
10ms< <200ms
Table 5. Reset time t
a
and Data valid time t
b.

AK4121AVF

Mfr. #:
Manufacturer:
Description:
IC SAMPLE RATE CONVERTER 24VSOP
Lifecycle:
New from this manufacturer.
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