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AK4121AVF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
[AK4121A]
MS0337-E-06
2010/04
- 16 -
SYSTEM DESIGN
Figure 13
and
Figure 14
illustrate typical
system connection diagrams.
The evaluation
board [AKD4121A]
demonstrates this applicatio
n circuit, the optimum layout, an
d power supply arrangement and performance
measurement results.
FILT
A
VSS
PDN
SMU
TE
DEM0
DEM1
ILRC
K
IBICK
SDTI
IDIF0
IDIF1
IDIF2
VDD
DVSS
TVDD
MCLK
OLRCK
OBICK
SDTO
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
AK4121A
10u
+
0.1u
+3.3~5V
Digital (*1)
0.1u
DSP1
1.0n
DSP2
Control
Mode
se
tt
ing
(fix to “H” or “L”)
4.7u
560
fsi
fso
+3.3
V Ana
log
Figure 13. Exa
mple of a ty
pical design
(Slave Mode)
FILT
A
VSS
PDN
SMU
TE
DEM0
DEM1
ILRC
K
IBICK
SDTI
IDIF0
IDIF1
IDIF2
VDD
DVSS
TVDD
MCLK
OLRCK
OBICK
SDTO
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
AK4121A
10u
+
0.1u
+3.3~5V
Digital (*1)
0.1u
DSP1
1.0n
DSP2
Control
Mode
se
tt
ing
(fix to “H” or “L”)
4.7u
560
fsi
fso
+3.3
V Ana
log
64fso
256fso
Figure 14. Exa
mple of a ty
pical design
(Master Mode;
MCLK=256fso)
*1. TVDD sh
ould be the sam
e as the m
aximum i
nput voltage.
[AK4121A]
MS0337-E-06
2010/04
- 17 -
PACKAGE
0.1
±
0.1
0-10
°
Detail
A
Seating Plane
NOTE
: Dim
ensi
on "*
" doe
s no
t
include m
old flas
h.
0.10
0.15
0.22
±
0.1
0.65
*7.9
±
0.2
1.25
±
0.2
A
1
12
13
24
24
p
in VSO
P
(
Uni
t: m
m
)
7.6
±
0.2
0.5
±
0.2
*5.6
±
0.2
+0.
1
-0.05
■
Package & Lead frame material
Package molding compound:
Epoxy
Lead
frame
material:
Cu
Lead frame surface treatm
ent:
Solder plate (Pb free)
[AK4121A]
MS0337-E-06
2010/04
- 18 -
MARKING
A
KM
A
K4121A
VF
A
A
XXX
X
Contents of
AAXXXX
AA:
Lot#
XXXX: Date
Code
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
AK4121AVF
Mfr. #:
Buy AK4121AVF
Manufacturer:
Description:
IC SAMPLE RATE CONVERTER 24VSOP
Lifecycle:
New from this manufacturer.
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AK4121AVF