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74SSTUA32866BFG
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
13
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
REGISTER TIMING
Timing Diagram for SSTUA32866 Used as a Single Device; C0 = 0, C1 = 0
RESET
DCS
CSR
CLK
CLK
D1 - D25
Q1 - Q25
PAR_IN
PPO
QERR
n
n + 1
n + 2
n
+ 3
n + 4
t
SU
t
H
t
PD
CLK t
o Q
t
SU
t
H
t
PD
t
PD
CLK t
o Q
CLK to Q
ERR
t
PD
CLK to Q
ERR
14
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
REGISTER TIMING
Timing Diagram for the First SSTUA32866 (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1
RESET
DCS
CSR
CLK
CLK
D1 - D14
Q1 - Q14
PAR_IN
PPO
QERR
(not
used)
n
n + 1
n
+ 2
n + 3
n + 4
t
SU
t
H
t
PD
CL
K to Q
t
SU
t
H
t
PD
t
PD
CLK to
PPO
CLK t
o
QE
RR
t
PD
CLK to QERR
15
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
REGISTER TIMING
Timing Diagram for the First SSTUA32866 (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1
RESET
DCS
CSR
CLK
CLK
D1 - D14
Q1 - Q14
PAR_IN
PPO
(not used)
QERR
n
n + 1
n + 2
n
+ 3
n + 4
t
SU
t
H
t
PD
CLK
to Q
t
SU
t
H
t
PD
t
PD
CLK
to PPO
CLK to
Q
ERR
t
PD
CLK to
Q
ERR
(1)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
74SSTUA32866BFG
Mfr. #:
Buy 74SSTUA32866BFG
Manufacturer:
IDT
Description:
Registers DDR II REGISTER
Lifecycle:
New from this manufacturer.
Delivery:
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