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74SSTUA32866BFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
4
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
PIN CONFIGURATION (TYPE A)
96-PIN LFBGA
1:2 REGISTER (TYPE A, FRONTSIDE)
TOP VIEW
PIN CONFIGURATION (TYPE B)
96-PIN LFBGA
1:2 REGISTER (TYPE B, BACKSIDE)
TOP VIEW
6
5
4
3
2
1
AB
C
DE F
G
HJ
K
LMNPRT
Q2B Q3B Q5B Q6B Q8B Q9B
NC
QCSB
QCSA
QODTBQCKEB
Q13B Q14B
V
DD
VREF
D2
D3
D5
D6
CLK
RESET
D8 D9
D10
D11
Q2A Q3A Q5A Q6A Q8A Q9A
NC
QODTAQCKEA
Q13A Q14A
PPO
CLK
C0
C1
V
DD
VREF
DCKE
DNU DNU QERR
DODT
GND
GND
V
DD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
DCS CSR
Q10B Q11B
Q10A Q11A
Q12B
Q12A
PAR_IN D12 D14
D13
DNU DNU DNU DNU DNU DNU DNU
DNU DNU
6
5
2
1
AB
C
DEF
G
H
J
K
LMNPRT
Q13B
Q10B
Q9BQ8BQCSB
QCSA
Q6BQ5B
NC
NC
QODTB QCKEBQ4BQ3BQ2BQ1B
D13D12
D9D8
D6D5
CLKD4D3
D2
D1
Q13A
Q10A
Q9AQ8AQ6AQ5A QODTA QCKEAQ4AQ3AQ2AQ1A
CLK
C0
C1
DCKEDODT
4
3
VDD
VREF
VDD
VREF
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
Q12B
Q12A
PAR_IN
D10
RESET
PPO DNU DNU QERR
DCS CSR
DNU DNU DNU DNU DNU DNU DNU
DNU DNU
5
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FUNCTIONAL BLOCK DIAGRAM (1:1)
RESET
CLK1
CLK1
V
REF
DCKE
DODT
DCS
CSR
QOTD
R
1D
C1
QCS
R
1D
C1
QCKE
R
1D
C1
TO 21 OTHER CHANNELS (D3, D5, D6, D8-D25)
D2
Q2
R
1D
C1
One of 22 Channels
0
1
6
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
PIN CONFIGURATION
96-PIN LFBGA
1:1 REGISTER
TOP VIEW
6
5
2
1
AB
C
DEF
G
HJ
K
LMNPRT
Q15 Q16
Q17 Q18
NCDNU
QCS
DNU Q19 Q20 Q21 Q22
D2
D3
D5
D6
CLK
RESET
D8 D9
D10
D11
Q2
Q3 Q5 Q6 NCQODTQCKE Q8 Q9 Q10 Q11
PPO
DCS
CLK
C0
C1
DCKE
QERR
DODT
DNU
D15
D16
D17
D18
D19 D20
D21
D22
4
3
VDD
VREF
VDD
VREF
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
CSR
Q23 Q24
Q25
Q12 Q13
Q14
D23 D24
D25
PAR_IN
D12 D13 D14
*Rows 3 and 4 are reserved for VDD and GND.
96 BALL LFBGA PACKAGE ATTRIBUTES
ABCDEFGHJKLMNPRT
6
5
4
3
2
1
Top
Marking
ABCDEFGHJKLMNPRT
6
5
4
3
2
1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74SSTUA32866BFG

Mfr. #:
Buy 74SSTUA32866BFG
Manufacturer:
IDT
Description:
Registers DDR II REGISTER
Lifecycle:
New from this manufacturer.
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